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Loading design for application trce from file cl202_mxo2_2000hc.ncd.
Design name: Top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-2000HE
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c2000.nph' in environment: C:/ToolSoftware/Diamond/3.14/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 36.4.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.14.0.75.2
Tue Nov 19 16:14:09 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2024 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o CL202_MXO2_2000HC.twr -gui -msgset D:/Light_Source/CPLD/CL202_B(I232O232-202107231608)/promote.xml CL202_MXO2_2000HC.ncd CL202_MXO2_2000HC.prf 
Design file:     cl202_mxo2_2000hc.ncd
Preference file: cl202_mxo2_2000hc.prf
Device,speed:    LCMXO2-2000HE,4
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

Report Type:     based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "Clk_c" 269.469000 MHz ;
            4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/Delay_set[5]  (to Clk_c +)
                   FF                        U5/Delay_set[4]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_165 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_165:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R4C13C.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_165:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R4C13C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/count_set[14]  (to Clk_c +)
                   FF                        U5/count_set[13]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_178 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_178:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R3C14D.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_178:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R3C14D.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/Delay_set[7]  (to Clk_c +)
                   FF                        U5/Delay_set[6]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_164 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_164:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R4C13D.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_164:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R4C13D.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/count_set[10]  (to Clk_c +)
                   FF                        U5/count_set[0]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_185 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_185:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R3C13A.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_185:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R3C13A.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/count_set[12]  (to Clk_c +)
                   FF                        U5/count_set[11]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_179 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_179:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R3C14C.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_179:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R3C14C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/Delay_set[14]  (to Clk_c +)
                   FF                        U5/Delay_set[13]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_160 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_160:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R4C14D.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_160:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R4C14D.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/Delay_set[10]  (to Clk_c +)
                   FF                        U5/Delay_set[0]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_167 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_167:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R4C13A.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_167:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R4C13A.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/Delay_set[12]  (to Clk_c +)
                   FF                        U5/Delay_set[11]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_161 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R4C14C.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R4C14C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/Delay_set[3]  (to Clk_c +)
                   FF                        U5/Delay_set[2]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_166 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_166:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R4C13B.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_166:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R4C13B.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.


Error: The following path exceeds requirements by 18.559ns (weighted slack = -372.284ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulse_EN  (from LaserPulse_Sig -)
   Destination:    FF         Data in        U5/count_set[7]  (to Clk_c +)
                   FF                        U5/count_set[6]

   Delay:               8.407ns  (17.2% logic, 82.8% route), 3 logic levels.

 Constraint Details:

      8.407ns physical path delay SLICE_209 to U5/SLICE_182 exceeds
      (delay constraint based on source clock period of 3.128ns and destination clock period of 3.711ns)
      0.185ns delay constraint less
     10.054ns skew and
      0.283ns CE_SET requirement (totaling -10.152ns) by 18.559ns

 Physical Path Details:

      Data path SLICE_209 to U5/SLICE_182:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R5C10A.CLK to      R5C10A.Q1 SLICE_209 (from LaserPulse_Sig)
ROUTE         2     1.530      R5C10A.Q1 to      R9C10D.A1 SPulse_EN
CTOF_DEL    ---     0.497      R9C10D.A1 to      R9C10D.F1 SLICE_409
ROUTE         1     1.953      R9C10D.F1 to      R2C12A.A1 LaserLed_0
CTOF_DEL    ---     0.497      R2C12A.A1 to      R2C12A.F1 SLICE_390
ROUTE        28     3.476      R2C12A.F1 to      R3C13D.CE PulseOut_c[0] (to Clk_c)
                  --------
                    8.407   (17.2% logic, 82.8% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_209:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to    R10C13B.CLK Clk_c
REG_DEL     ---     0.454    R10C13B.CLK to     R10C13B.Q0 U3/SLICE_45
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
REG_DEL     ---     0.454     R11C5B.CLK to      R11C5B.Q0 U3/SLICE_272
ROUTE         2     2.581      R11C5B.Q0 to      R2C12A.B0 LED_c[0]
CTOF_DEL    ---     0.497      R2C12A.B0 to      R2C12A.F0 SLICE_390
ROUTE        11     3.285      R2C12A.F0 to     R5C10A.CLK LaserPulse_Sig
                  --------
                   15.701   (16.4% logic, 83.6% route), 4 logic levels.

      Destination Clock Path Clk to U5/SLICE_182:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R3C13D.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

Warning:   2.660MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "Clk_Count[16]" 399.840000 MHz ;
            109 items scored, 104 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 4.156ns (weighted slack = -128.323ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[6]  (to Clk_Count[16] +)

   Delay:               6.439ns  (38.1% logic, 61.9% route), 5 logic levels.

 Constraint Details:

      6.439ns physical path delay SLICE_277 to SLICE_237 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.166ns DIN_SET requirement (totaling 2.283ns) by 4.156ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.986      R9C15C.Q0 to      R9C14A.B0 TB_watchdog
C0TOFCO_DE  ---     1.029      R9C14A.B0 to     R9C14A.FCO SLICE_240
ROUTE         1     0.000     R9C14A.FCO to     R9C14B.FCI TB_watchdog_cry[0]
FCITOFCO_D  ---     0.162     R9C14B.FCI to     R9C14B.FCO SLICE_239
ROUTE         1     0.000     R9C14B.FCO to     R9C14C.FCI TB_watchdog_cry[2]
FCITOFCO_D  ---     0.162     R9C14C.FCI to     R9C14C.FCO SLICE_238
ROUTE         1     0.000     R9C14C.FCO to     R9C14D.FCI TB_watchdog_cry[4]
FCITOF1_DE  ---     0.646     R9C14D.FCI to      R9C14D.F1 SLICE_237
ROUTE         1     0.000      R9C14D.F1 to     R9C14D.DI1 TB_watchdog_s[6] (to Clk_Count[16])
                  --------
                    6.439   (38.1% logic, 61.9% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 4.098ns (weighted slack = -126.532ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[5]  (to Clk_Count[16] +)

   Delay:               6.381ns  (37.5% logic, 62.5% route), 5 logic levels.

 Constraint Details:

      6.381ns physical path delay SLICE_277 to SLICE_237 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.166ns DIN_SET requirement (totaling 2.283ns) by 4.098ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.986      R9C15C.Q0 to      R9C14A.B0 TB_watchdog
C0TOFCO_DE  ---     1.029      R9C14A.B0 to     R9C14A.FCO SLICE_240
ROUTE         1     0.000     R9C14A.FCO to     R9C14B.FCI TB_watchdog_cry[0]
FCITOFCO_D  ---     0.162     R9C14B.FCI to     R9C14B.FCO SLICE_239
ROUTE         1     0.000     R9C14B.FCO to     R9C14C.FCI TB_watchdog_cry[2]
FCITOFCO_D  ---     0.162     R9C14C.FCI to     R9C14C.FCO SLICE_238
ROUTE         1     0.000     R9C14C.FCO to     R9C14D.FCI TB_watchdog_cry[4]
FCITOF0_DE  ---     0.588     R9C14D.FCI to      R9C14D.F0 SLICE_237
ROUTE         1     0.000      R9C14D.F0 to     R9C14D.DI0 TB_watchdog_s[5] (to Clk_Count[16])
                  --------
                    6.381   (37.5% logic, 62.5% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 3.998ns (weighted slack = -123.444ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[6]  (to Clk_Count[16] +)

   Delay:               6.281ns  (36.9% logic, 63.1% route), 5 logic levels.

 Constraint Details:

      6.281ns physical path delay SLICE_277 to SLICE_237 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.166ns DIN_SET requirement (totaling 2.283ns) by 3.998ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.963      R9C15C.Q0 to      R9C14A.A1 TB_watchdog
C1TOFCO_DE  ---     0.894      R9C14A.A1 to     R9C14A.FCO SLICE_240
ROUTE         1     0.000     R9C14A.FCO to     R9C14B.FCI TB_watchdog_cry[0]
FCITOFCO_D  ---     0.162     R9C14B.FCI to     R9C14B.FCO SLICE_239
ROUTE         1     0.000     R9C14B.FCO to     R9C14C.FCI TB_watchdog_cry[2]
FCITOFCO_D  ---     0.162     R9C14C.FCI to     R9C14C.FCO SLICE_238
ROUTE         1     0.000     R9C14C.FCO to     R9C14D.FCI TB_watchdog_cry[4]
FCITOF1_DE  ---     0.646     R9C14D.FCI to      R9C14D.F1 SLICE_237
ROUTE         1     0.000      R9C14D.F1 to     R9C14D.DI1 TB_watchdog_s[6] (to Clk_Count[16])
                  --------
                    6.281   (36.9% logic, 63.1% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 3.994ns (weighted slack = -123.321ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[4]  (to Clk_Count[16] +)

   Delay:               6.277ns  (36.5% logic, 63.5% route), 4 logic levels.

 Constraint Details:

      6.277ns physical path delay SLICE_277 to SLICE_238 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.166ns DIN_SET requirement (totaling 2.283ns) by 3.994ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.986      R9C15C.Q0 to      R9C14A.B0 TB_watchdog
C0TOFCO_DE  ---     1.029      R9C14A.B0 to     R9C14A.FCO SLICE_240
ROUTE         1     0.000     R9C14A.FCO to     R9C14B.FCI TB_watchdog_cry[0]
FCITOFCO_D  ---     0.162     R9C14B.FCI to     R9C14B.FCO SLICE_239
ROUTE         1     0.000     R9C14B.FCO to     R9C14C.FCI TB_watchdog_cry[2]
FCITOF1_DE  ---     0.646     R9C14C.FCI to      R9C14C.F1 SLICE_238
ROUTE         1     0.000      R9C14C.F1 to     R9C14C.DI1 TB_watchdog_s[4] (to Clk_Count[16])
                  --------
                    6.277   (36.5% logic, 63.5% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14C.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 3.957ns (weighted slack = -122.178ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[6]  (to Clk_Count[16] +)

   Delay:               6.240ns  (36.7% logic, 63.3% route), 4 logic levels.

 Constraint Details:

      6.240ns physical path delay SLICE_277 to SLICE_237 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.166ns DIN_SET requirement (totaling 2.283ns) by 3.957ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.949      R9C15C.Q0 to      R9C14B.A0 TB_watchdog
C0TOFCO_DE  ---     1.029      R9C14B.A0 to     R9C14B.FCO SLICE_239
ROUTE         1     0.000     R9C14B.FCO to     R9C14C.FCI TB_watchdog_cry[2]
FCITOFCO_D  ---     0.162     R9C14C.FCI to     R9C14C.FCO SLICE_238
ROUTE         1     0.000     R9C14C.FCO to     R9C14D.FCI TB_watchdog_cry[4]
FCITOF1_DE  ---     0.646     R9C14D.FCI to      R9C14D.F1 SLICE_237
ROUTE         1     0.000      R9C14D.F1 to     R9C14D.DI1 TB_watchdog_s[6] (to Clk_Count[16])
                  --------
                    6.240   (36.7% logic, 63.3% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 3.940ns (weighted slack = -121.654ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[5]  (to Clk_Count[16] +)

   Delay:               6.223ns  (36.3% logic, 63.7% route), 5 logic levels.

 Constraint Details:

      6.223ns physical path delay SLICE_277 to SLICE_237 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.166ns DIN_SET requirement (totaling 2.283ns) by 3.940ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.963      R9C15C.Q0 to      R9C14A.A1 TB_watchdog
C1TOFCO_DE  ---     0.894      R9C14A.A1 to     R9C14A.FCO SLICE_240
ROUTE         1     0.000     R9C14A.FCO to     R9C14B.FCI TB_watchdog_cry[0]
FCITOFCO_D  ---     0.162     R9C14B.FCI to     R9C14B.FCO SLICE_239
ROUTE         1     0.000     R9C14B.FCO to     R9C14C.FCI TB_watchdog_cry[2]
FCITOFCO_D  ---     0.162     R9C14C.FCI to     R9C14C.FCO SLICE_238
ROUTE         1     0.000     R9C14C.FCO to     R9C14D.FCI TB_watchdog_cry[4]
FCITOF0_DE  ---     0.588     R9C14D.FCI to      R9C14D.F0 SLICE_237
ROUTE         1     0.000      R9C14D.F0 to     R9C14D.DI0 TB_watchdog_s[5] (to Clk_Count[16])
                  --------
                    6.223   (36.3% logic, 63.7% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 3.936ns (weighted slack = -121.530ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[3]  (to Clk_Count[16] +)

   Delay:               6.219ns  (35.9% logic, 64.1% route), 4 logic levels.

 Constraint Details:

      6.219ns physical path delay SLICE_277 to SLICE_238 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.166ns DIN_SET requirement (totaling 2.283ns) by 3.936ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.986      R9C15C.Q0 to      R9C14A.B0 TB_watchdog
C0TOFCO_DE  ---     1.029      R9C14A.B0 to     R9C14A.FCO SLICE_240
ROUTE         1     0.000     R9C14A.FCO to     R9C14B.FCI TB_watchdog_cry[0]
FCITOFCO_D  ---     0.162     R9C14B.FCI to     R9C14B.FCO SLICE_239
ROUTE         1     0.000     R9C14B.FCO to     R9C14C.FCI TB_watchdog_cry[2]
FCITOF0_DE  ---     0.588     R9C14C.FCI to      R9C14C.F0 SLICE_238
ROUTE         1     0.000      R9C14C.F0 to     R9C14C.DI0 TB_watchdog_s[3] (to Clk_Count[16])
                  --------
                    6.219   (35.9% logic, 64.1% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14C.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 3.899ns (weighted slack = -120.388ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[5]  (to Clk_Count[16] +)

   Delay:               6.182ns  (36.1% logic, 63.9% route), 4 logic levels.

 Constraint Details:

      6.182ns physical path delay SLICE_277 to SLICE_237 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.166ns DIN_SET requirement (totaling 2.283ns) by 3.899ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.949      R9C15C.Q0 to      R9C14B.A0 TB_watchdog
C0TOFCO_DE  ---     1.029      R9C14B.A0 to     R9C14B.FCO SLICE_239
ROUTE         1     0.000     R9C14B.FCO to     R9C14C.FCI TB_watchdog_cry[2]
FCITOFCO_D  ---     0.162     R9C14C.FCI to     R9C14C.FCO SLICE_238
ROUTE         1     0.000     R9C14C.FCO to     R9C14D.FCI TB_watchdog_cry[4]
FCITOF0_DE  ---     0.588     R9C14D.FCI to      R9C14D.F0 SLICE_237
ROUTE         1     0.000      R9C14D.F0 to     R9C14D.DI0 TB_watchdog_s[5] (to Clk_Count[16])
                  --------
                    6.182   (36.1% logic, 63.9% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 3.862ns (weighted slack = -119.245ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[6]  (to Clk_Count[16] +)
                   FF                        TB_watchdog[5]

   Delay:               6.028ns  (15.8% logic, 84.2% route), 2 logic levels.

 Constraint Details:

      6.028ns physical path delay SLICE_277 to SLICE_237 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.283ns CE_SET requirement (totaling 2.166ns) by 3.862ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.949      R9C15C.Q0 to      R9C15C.A1 TB_watchdog
CTOF_DEL    ---     0.497      R9C15C.A1 to      R9C15C.F1 SLICE_277
ROUTE         5     1.128      R9C15C.F1 to      R9C14D.CE TB_watchdoge (to Clk_Count[16])
                  --------
                    6.028   (15.8% logic, 84.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.


Error: The following path exceeds requirements by 3.862ns (weighted slack = -119.245ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[4]  (to Clk_Count[16] +)
                   FF                        TB_watchdog[3]

   Delay:               6.028ns  (15.8% logic, 84.2% route), 2 logic levels.

 Constraint Details:

      6.028ns physical path delay SLICE_277 to SLICE_238 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -2.368ns skew and
      0.283ns CE_SET requirement (totaling 2.166ns) by 3.862ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     3.949      R9C15C.Q0 to      R9C15C.A1 TB_watchdog
CTOF_DEL    ---     0.497      R9C15C.A1 to      R9C15C.F1 SLICE_277
ROUTE         5     1.128      R9C15C.F1 to      R9C14C.CE TB_watchdoge (to Clk_Count[16])
                  --------
                    6.028   (15.8% logic, 84.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.454      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     1.914       R9C4A.Q1 to     R9C14C.CLK Clk_Count[16]
                  --------
                    8.015   (20.2% logic, 79.8% route), 2 logic levels.

Warning:   7.644MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "un3_tb_pluse_q2_buf" 399.840000 MHz ;
            1 item scored, 1 timing error detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 0.561ns (weighted slack = -17.322ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U5/Q  (from Clk_c +)
   Destination:    FF         Data in        SPulse_Check  (to un3_tb_pluse_q2_buf +)

   Delay:               2.943ns  (15.4% logic, 84.6% route), 1 logic levels.

 Constraint Details:

      2.943ns physical path delay U5/SLICE_275 to SLICE_274 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.081ns delay constraint less
     -3.038ns skew and
      0.737ns LSRREC_SET requirement (totaling 2.382ns) by 0.561ns

 Physical Path Details:

      Data path U5/SLICE_275 to SLICE_274:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R9C15D.CLK to      R9C15D.Q0 U5/SLICE_275 (from Clk_c)
ROUTE        20     2.489      R9C15D.Q0 to    R11C13B.LSR TB_Pluse_Q1 (to un3_tb_pluse_q2_buf)
                  --------
                    2.943   (15.4% logic, 84.6% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to U5/SLICE_275:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15D.CLK Clk_c
                  --------
                    5.647   (20.6% logic, 79.4% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_274:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.163         31.PAD to       31.PADDI Clk
ROUTE       138     4.484       31.PADDI to     R9C15B.CLK Clk_c
REG_DEL     ---     0.454     R9C15B.CLK to      R9C15B.Q0 U6/SLICE_276
ROUTE        20     1.473      R9C15B.Q0 to     R11C13D.B1 TB_Pluse_Q2
CTOF_DEL    ---     0.497     R11C13D.B1 to     R11C13D.F1 SLICE_338
ROUTE         1     0.614     R11C13D.F1 to    R11C13B.CLK un3_tb_pluse_q2_buf
                  --------
                    8.685   (24.3% logic, 75.7% route), 3 logic levels.

Warning:  50.446MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "U3/Clk_10ms[17]" 335.909000 MHz ;
            84 items scored, 58 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 3.388ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[0]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Stop_sig  (to U3/Clk_10ms[17] +)

   Delay:               6.199ns  (48.0% logic, 52.0% route), 7 logic levels.

 Constraint Details:

      6.199ns physical path delay U3/SLICE_59 to U3/SLICE_272 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.811ns) by 3.388ns

 Physical Path Details:

      Data path U3/SLICE_59 to U3/SLICE_272:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4A.CLK to      R11C4A.Q1 U3/SLICE_59 (from U3/Clk_10ms[17])
ROUTE         2     2.180      R11C4A.Q1 to      R10C4A.B1 U3/Count_stop[0]
C1TOFCO_DE  ---     0.894      R10C4A.B1 to     R10C4A.FCO SLICE_31
ROUTE         1     0.000     R10C4A.FCO to     R10C4B.FCI U3/count_stop_cry_0
FCITOFCO_D  ---     0.162     R10C4B.FCI to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.042      R10C5A.F1 to      R11C5B.B0 U3/count_stop
CTOF_DEL    ---     0.497      R11C5B.B0 to      R11C5B.F0 U3/SLICE_272
ROUTE         1     0.000      R11C5B.F0 to     R11C5B.DI0 U3/count_stop_i (to U3/Clk_10ms[17])
                  --------
                    6.199   (48.0% logic, 52.0% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_272:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.104ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[0]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[2]  (to U3/Clk_10ms[17] +)
                   FF                        U3/Count_stop[1]

   Delay:               5.798ns  (42.8% logic, 57.2% route), 6 logic levels.

 Constraint Details:

      5.798ns physical path delay U3/SLICE_59 to U3/SLICE_58 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.283ns CE_SET requirement (totaling 2.694ns) by 3.104ns

 Physical Path Details:

      Data path U3/SLICE_59 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4A.CLK to      R11C4A.Q1 U3/SLICE_59 (from U3/Clk_10ms[17])
ROUTE         2     2.180      R11C4A.Q1 to      R10C4A.B1 U3/Count_stop[0]
C1TOFCO_DE  ---     0.894      R10C4A.B1 to     R10C4A.FCO SLICE_31
ROUTE         1     0.000     R10C4A.FCO to     R10C4B.FCI U3/count_stop_cry_0
FCITOFCO_D  ---     0.162     R10C4B.FCI to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.138      R10C5A.F1 to      R11C4B.CE U3/count_stop (to U3/Clk_10ms[17])
                  --------
                    5.798   (42.8% logic, 57.2% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.104ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[0]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[6]  (to U3/Clk_10ms[17] +)
                   FF                        U3/Count_stop[5]

   Delay:               5.798ns  (42.8% logic, 57.2% route), 6 logic levels.

 Constraint Details:

      5.798ns physical path delay U3/SLICE_59 to U3/SLICE_56 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.283ns CE_SET requirement (totaling 2.694ns) by 3.104ns

 Physical Path Details:

      Data path U3/SLICE_59 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4A.CLK to      R11C4A.Q1 U3/SLICE_59 (from U3/Clk_10ms[17])
ROUTE         2     2.180      R11C4A.Q1 to      R10C4A.B1 U3/Count_stop[0]
C1TOFCO_DE  ---     0.894      R10C4A.B1 to     R10C4A.FCO SLICE_31
ROUTE         1     0.000     R10C4A.FCO to     R10C4B.FCI U3/count_stop_cry_0
FCITOFCO_D  ---     0.162     R10C4B.FCI to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.138      R10C5A.F1 to      R11C4D.CE U3/count_stop (to U3/Clk_10ms[17])
                  --------
                    5.798   (42.8% logic, 57.2% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4D.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.104ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[0]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[4]  (to U3/Clk_10ms[17] +)
                   FF                        U3/Count_stop[3]

   Delay:               5.798ns  (42.8% logic, 57.2% route), 6 logic levels.

 Constraint Details:

      5.798ns physical path delay U3/SLICE_59 to U3/SLICE_57 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.283ns CE_SET requirement (totaling 2.694ns) by 3.104ns

 Physical Path Details:

      Data path U3/SLICE_59 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4A.CLK to      R11C4A.Q1 U3/SLICE_59 (from U3/Clk_10ms[17])
ROUTE         2     2.180      R11C4A.Q1 to      R10C4A.B1 U3/Count_stop[0]
C1TOFCO_DE  ---     0.894      R10C4A.B1 to     R10C4A.FCO SLICE_31
ROUTE         1     0.000     R10C4A.FCO to     R10C4B.FCI U3/count_stop_cry_0
FCITOFCO_D  ---     0.162     R10C4B.FCI to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.138      R10C5A.F1 to      R11C4C.CE U3/count_stop (to U3/Clk_10ms[17])
                  --------
                    5.798   (42.8% logic, 57.2% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4C.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.104ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[0]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[0]  (to U3/Clk_10ms[17] +)

   Delay:               5.798ns  (42.8% logic, 57.2% route), 6 logic levels.

 Constraint Details:

      5.798ns physical path delay U3/SLICE_59 to U3/SLICE_59 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.283ns CE_SET requirement (totaling 2.694ns) by 3.104ns

 Physical Path Details:

      Data path U3/SLICE_59 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4A.CLK to      R11C4A.Q1 U3/SLICE_59 (from U3/Clk_10ms[17])
ROUTE         2     2.180      R11C4A.Q1 to      R10C4A.B1 U3/Count_stop[0]
C1TOFCO_DE  ---     0.894      R10C4A.B1 to     R10C4A.FCO SLICE_31
ROUTE         1     0.000     R10C4A.FCO to     R10C4B.FCI U3/count_stop_cry_0
FCITOFCO_D  ---     0.162     R10C4B.FCI to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.138      R10C5A.F1 to      R11C4A.CE U3/count_stop (to U3/Clk_10ms[17])
                  --------
                    5.798   (42.8% logic, 57.2% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.094ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[1]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Stop_sig  (to U3/Clk_10ms[17] +)

   Delay:               5.905ns  (50.0% logic, 50.0% route), 6 logic levels.

 Constraint Details:

      5.905ns physical path delay U3/SLICE_58 to U3/SLICE_272 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.811ns) by 3.094ns

 Physical Path Details:

      Data path U3/SLICE_58 to U3/SLICE_272:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4B.CLK to      R11C4B.Q0 U3/SLICE_58 (from U3/Clk_10ms[17])
ROUTE         2     1.913      R11C4B.Q0 to      R10C4B.A0 U3/Count_stop[1]
C0TOFCO_DE  ---     1.029      R10C4B.A0 to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.042      R10C5A.F1 to      R11C5B.B0 U3/count_stop
CTOF_DEL    ---     0.497      R11C5B.B0 to      R11C5B.F0 U3/SLICE_272
ROUTE         1     0.000      R11C5B.F0 to     R11C5B.DI0 U3/count_stop_i (to U3/Clk_10ms[17])
                  --------
                    5.905   (50.0% logic, 50.0% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_272:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C5B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.810ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[1]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[0]  (to U3/Clk_10ms[17] +)

   Delay:               5.504ns  (44.6% logic, 55.4% route), 5 logic levels.

 Constraint Details:

      5.504ns physical path delay U3/SLICE_58 to U3/SLICE_59 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.283ns CE_SET requirement (totaling 2.694ns) by 2.810ns

 Physical Path Details:

      Data path U3/SLICE_58 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4B.CLK to      R11C4B.Q0 U3/SLICE_58 (from U3/Clk_10ms[17])
ROUTE         2     1.913      R11C4B.Q0 to      R10C4B.A0 U3/Count_stop[1]
C0TOFCO_DE  ---     1.029      R10C4B.A0 to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.138      R10C5A.F1 to      R11C4A.CE U3/count_stop (to U3/Clk_10ms[17])
                  --------
                    5.504   (44.6% logic, 55.4% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.810ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[1]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[4]  (to U3/Clk_10ms[17] +)
                   FF                        U3/Count_stop[3]

   Delay:               5.504ns  (44.6% logic, 55.4% route), 5 logic levels.

 Constraint Details:

      5.504ns physical path delay U3/SLICE_58 to U3/SLICE_57 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.283ns CE_SET requirement (totaling 2.694ns) by 2.810ns

 Physical Path Details:

      Data path U3/SLICE_58 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4B.CLK to      R11C4B.Q0 U3/SLICE_58 (from U3/Clk_10ms[17])
ROUTE         2     1.913      R11C4B.Q0 to      R10C4B.A0 U3/Count_stop[1]
C0TOFCO_DE  ---     1.029      R10C4B.A0 to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.138      R10C5A.F1 to      R11C4C.CE U3/count_stop (to U3/Clk_10ms[17])
                  --------
                    5.504   (44.6% logic, 55.4% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4C.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.810ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[1]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[2]  (to U3/Clk_10ms[17] +)
                   FF                        U3/Count_stop[1]

   Delay:               5.504ns  (44.6% logic, 55.4% route), 5 logic levels.

 Constraint Details:

      5.504ns physical path delay U3/SLICE_58 to U3/SLICE_58 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.283ns CE_SET requirement (totaling 2.694ns) by 2.810ns

 Physical Path Details:

      Data path U3/SLICE_58 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4B.CLK to      R11C4B.Q0 U3/SLICE_58 (from U3/Clk_10ms[17])
ROUTE         2     1.913      R11C4B.Q0 to      R10C4B.A0 U3/Count_stop[1]
C0TOFCO_DE  ---     1.029      R10C4B.A0 to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.138      R10C5A.F1 to      R11C4B.CE U3/count_stop (to U3/Clk_10ms[17])
                  --------
                    5.504   (44.6% logic, 55.4% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.810ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[1]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[6]  (to U3/Clk_10ms[17] +)
                   FF                        U3/Count_stop[5]

   Delay:               5.504ns  (44.6% logic, 55.4% route), 5 logic levels.

 Constraint Details:

      5.504ns physical path delay U3/SLICE_58 to U3/SLICE_56 exceeds
      2.977ns delay constraint less
      0.000ns skew and
      0.283ns CE_SET requirement (totaling 2.694ns) by 2.810ns

 Physical Path Details:

      Data path U3/SLICE_58 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R11C4B.CLK to      R11C4B.Q0 U3/SLICE_58 (from U3/Clk_10ms[17])
ROUTE         2     1.913      R11C4B.Q0 to      R10C4B.A0 U3/Count_stop[1]
C0TOFCO_DE  ---     1.029      R10C4B.A0 to     R10C4B.FCO SLICE_30
ROUTE         1     0.000     R10C4B.FCO to     R10C4C.FCI U3/count_stop_cry_2
FCITOFCO_D  ---     0.162     R10C4C.FCI to     R10C4C.FCO SLICE_29
ROUTE         1     0.000     R10C4C.FCO to     R10C4D.FCI U3/count_stop_cry_4
FCITOFCO_D  ---     0.162     R10C4D.FCI to     R10C4D.FCO U3/SLICE_28
ROUTE         1     0.000     R10C4D.FCO to     R10C5A.FCI U3/count_stop_cry_6
FCITOF1_DE  ---     0.646     R10C5A.FCI to      R10C5A.F1 U3/SLICE_27
ROUTE         6     1.138      R10C5A.F1 to      R11C4D.CE U3/count_stop (to U3/Clk_10ms[17])
                  --------
                    5.504   (44.6% logic, 55.4% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     2.783     R10C13B.Q0 to     R11C4D.CLK U3/Clk_10ms[17]
                  --------
                    2.783   (0.0% logic, 100.0% route), 0 logic levels.

Warning: 157.109MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "LaserPulse_Sig" 319.693000 MHz ;
            296 items scored, 215 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 2.871ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[0]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[14]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[13]

   Delay:               5.691ns  (55.0% logic, 45.0% route), 10 logic levels.

 Constraint Details:

      5.691ns physical path delay SLICE_226 to SLICE_219 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.871ns

 Physical Path Details:

      Data path SLICE_226 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8A.CLK to       R4C8A.Q1 SLICE_226 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8A.Q1 to       R5C8A.A1 SPulseCount[0]
C1TOFCO_DE  ---     0.894       R5C8A.A1 to      R5C8A.FCO SLICE_217
ROUTE         1     0.000      R5C8A.FCO to      R5C8B.FCI spulsecount_cry_0
FCITOFCO_D  ---     0.162      R5C8B.FCI to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C9D.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.691   (55.0% logic, 45.0% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C9D.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.871ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[0]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[12]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[11]

   Delay:               5.691ns  (55.0% logic, 45.0% route), 10 logic levels.

 Constraint Details:

      5.691ns physical path delay SLICE_226 to SLICE_220 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.871ns

 Physical Path Details:

      Data path SLICE_226 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8A.CLK to       R4C8A.Q1 SLICE_226 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8A.Q1 to       R5C8A.A1 SPulseCount[0]
C1TOFCO_DE  ---     0.894       R5C8A.A1 to      R5C8A.FCO SLICE_217
ROUTE         1     0.000      R5C8A.FCO to      R5C8B.FCI spulsecount_cry_0
FCITOFCO_D  ---     0.162      R5C8B.FCI to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C9C.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.691   (55.0% logic, 45.0% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C9C.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.871ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[0]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[10]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[9]

   Delay:               5.691ns  (55.0% logic, 45.0% route), 10 logic levels.

 Constraint Details:

      5.691ns physical path delay SLICE_226 to SLICE_221 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.871ns

 Physical Path Details:

      Data path SLICE_226 to SLICE_221:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8A.CLK to       R4C8A.Q1 SLICE_226 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8A.Q1 to       R5C8A.A1 SPulseCount[0]
C1TOFCO_DE  ---     0.894       R5C8A.A1 to      R5C8A.FCO SLICE_217
ROUTE         1     0.000      R5C8A.FCO to      R5C8B.FCI spulsecount_cry_0
FCITOFCO_D  ---     0.162      R5C8B.FCI to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C9B.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.691   (55.0% logic, 45.0% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_221:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C9B.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.871ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[0]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[8]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[7]

   Delay:               5.691ns  (55.0% logic, 45.0% route), 10 logic levels.

 Constraint Details:

      5.691ns physical path delay SLICE_226 to SLICE_222 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.871ns

 Physical Path Details:

      Data path SLICE_226 to SLICE_222:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8A.CLK to       R4C8A.Q1 SLICE_226 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8A.Q1 to       R5C8A.A1 SPulseCount[0]
C1TOFCO_DE  ---     0.894       R5C8A.A1 to      R5C8A.FCO SLICE_217
ROUTE         1     0.000      R5C8A.FCO to      R5C8B.FCI spulsecount_cry_0
FCITOFCO_D  ---     0.162      R5C8B.FCI to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C9A.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.691   (55.0% logic, 45.0% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_222:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C9A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.871ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[0]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[6]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[5]

   Delay:               5.691ns  (55.0% logic, 45.0% route), 10 logic levels.

 Constraint Details:

      5.691ns physical path delay SLICE_226 to SLICE_223 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.871ns

 Physical Path Details:

      Data path SLICE_226 to SLICE_223:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8A.CLK to       R4C8A.Q1 SLICE_226 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8A.Q1 to       R5C8A.A1 SPulseCount[0]
C1TOFCO_DE  ---     0.894       R5C8A.A1 to      R5C8A.FCO SLICE_217
ROUTE         1     0.000      R5C8A.FCO to      R5C8B.FCI spulsecount_cry_0
FCITOFCO_D  ---     0.162      R5C8B.FCI to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C8D.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.691   (55.0% logic, 45.0% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_223:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8D.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.871ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[0]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[4]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[3]

   Delay:               5.691ns  (55.0% logic, 45.0% route), 10 logic levels.

 Constraint Details:

      5.691ns physical path delay SLICE_226 to SLICE_224 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.871ns

 Physical Path Details:

      Data path SLICE_226 to SLICE_224:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8A.CLK to       R4C8A.Q1 SLICE_226 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8A.Q1 to       R5C8A.A1 SPulseCount[0]
C1TOFCO_DE  ---     0.894       R5C8A.A1 to      R5C8A.FCO SLICE_217
ROUTE         1     0.000      R5C8A.FCO to      R5C8B.FCI spulsecount_cry_0
FCITOFCO_D  ---     0.162      R5C8B.FCI to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C8C.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.691   (55.0% logic, 45.0% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_224:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8C.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.871ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[0]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[2]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[1]

   Delay:               5.691ns  (55.0% logic, 45.0% route), 10 logic levels.

 Constraint Details:

      5.691ns physical path delay SLICE_226 to SLICE_225 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.871ns

 Physical Path Details:

      Data path SLICE_226 to SLICE_225:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8A.CLK to       R4C8A.Q1 SLICE_226 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8A.Q1 to       R5C8A.A1 SPulseCount[0]
C1TOFCO_DE  ---     0.894       R5C8A.A1 to      R5C8A.FCO SLICE_217
ROUTE         1     0.000      R5C8A.FCO to      R5C8B.FCI spulsecount_cry_0
FCITOFCO_D  ---     0.162      R5C8B.FCI to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C8B.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.691   (55.0% logic, 45.0% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_225:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8B.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.871ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[0]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[0]  (to LaserPulse_Sig -)

   Delay:               5.691ns  (55.0% logic, 45.0% route), 10 logic levels.

 Constraint Details:

      5.691ns physical path delay SLICE_226 to SLICE_226 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.871ns

 Physical Path Details:

      Data path SLICE_226 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8A.CLK to       R4C8A.Q1 SLICE_226 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8A.Q1 to       R5C8A.A1 SPulseCount[0]
C1TOFCO_DE  ---     0.894       R5C8A.A1 to      R5C8A.FCO SLICE_217
ROUTE         1     0.000      R5C8A.FCO to      R5C8B.FCI spulsecount_cry_0
FCITOFCO_D  ---     0.162      R5C8B.FCI to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C8A.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.691   (55.0% logic, 45.0% route), 10 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_226:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8A.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.844ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[1]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[14]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[13]

   Delay:               5.664ns  (54.7% logic, 45.3% route), 9 logic levels.

 Constraint Details:

      5.664ns physical path delay SLICE_225 to SLICE_219 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.844ns

 Physical Path Details:

      Data path SLICE_225 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8B.CLK to       R4C8B.Q0 SLICE_225 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8B.Q0 to       R5C8B.A0 SPulseCount[1]
C0TOFCO_DE  ---     1.029       R5C8B.A0 to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C9D.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.664   (54.7% logic, 45.3% route), 9 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_225:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8B.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C9D.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.844ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[1]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[12]  (to LaserPulse_Sig -)
                   FF                        SPulseCount[11]

   Delay:               5.664ns  (54.7% logic, 45.3% route), 9 logic levels.

 Constraint Details:

      5.664ns physical path delay SLICE_225 to SLICE_220 exceeds
      3.128ns delay constraint less
      0.000ns skew and
      0.308ns CE_SET requirement (totaling 2.820ns) by 2.844ns

 Physical Path Details:

      Data path SLICE_225 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R4C8B.CLK to       R4C8B.Q0 SLICE_225 (from LaserPulse_Sig)
ROUTE         2     1.398       R4C8B.Q0 to       R5C8B.A0 SPulseCount[1]
C0TOFCO_DE  ---     1.029       R5C8B.A0 to      R5C8B.FCO SLICE_216
ROUTE         1     0.000      R5C8B.FCO to      R5C8C.FCI spulsecount_cry_2
FCITOFCO_D  ---     0.162      R5C8C.FCI to      R5C8C.FCO SLICE_215
ROUTE         1     0.000      R5C8C.FCO to      R5C8D.FCI spulsecount_cry_4
FCITOFCO_D  ---     0.162      R5C8D.FCI to      R5C8D.FCO SLICE_214
ROUTE         1     0.000      R5C8D.FCO to      R5C9A.FCI spulsecount_cry_6
FCITOFCO_D  ---     0.162      R5C9A.FCI to      R5C9A.FCO SLICE_213
ROUTE         1     0.000      R5C9A.FCO to      R5C9B.FCI spulsecount_cry_8
FCITOFCO_D  ---     0.162      R5C9B.FCI to      R5C9B.FCO SLICE_212
ROUTE         1     0.000      R5C9B.FCO to      R5C9C.FCI spulsecount_cry_10
FCITOFCO_D  ---     0.162      R5C9C.FCI to      R5C9C.FCO SLICE_211
ROUTE         1     0.000      R5C9C.FCO to      R5C9D.FCI spulsecount_cry_12
FCITOFCO_D  ---     0.162      R5C9D.FCI to      R5C9D.FCO SLICE_210
ROUTE         1     0.000      R5C9D.FCO to     R5C10A.FCI spulsecount_cry_14
FCITOF1_DE  ---     0.646     R5C10A.FCI to      R5C10A.F1 SLICE_209
ROUTE        10     1.165      R5C10A.F1 to       R4C9C.CE spulsecount (to LaserPulse_Sig)
                  --------
                    5.664   (54.7% logic, 45.3% route), 9 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_225:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C8B.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     3.285      R2C12A.F0 to      R4C9C.CLK LaserPulse_Sig
                  --------
                    3.285   (0.0% logic, 100.0% route), 0 logic levels.

Warning: 166.694MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "Clk_Count[13]" 327.439000 MHz ;
            88 items scored, 32 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 3.694ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[7]  (to Clk_Count[13] +)

   Delay:               6.582ns  (46.4% logic, 53.6% route), 7 logic levels.

 Constraint Details:

      6.582ns physical path delay U1/SLICE_204 to U1/SLICE_204 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 3.694ns

 Physical Path Details:

      Data path U1/SLICE_204 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454    R11C13A.CLK to     R11C13A.Q0 U1/SLICE_204 (from Clk_Count[13])
ROUTE         3     1.538     R11C13A.Q0 to      R7C13D.A1 KEY_NonShake[0]
CTOF_DEL    ---     0.497      R7C13D.A1 to      R7C13D.F1 SLICE_386
ROUTE         1     1.990      R7C13D.F1 to     R11C12A.B0 U1/KEY_NonShake_i[0]
C0TOFCO_DE  ---     1.029     R11C12A.B0 to    R11C12A.FCO U1/SLICE_208
ROUTE         1     0.000    R11C12A.FCO to    R11C12B.FCI U1/un1_Count_1_cry_0
FCITOFCO_D  ---     0.162    R11C12B.FCI to    R11C12B.FCO U1/SLICE_207
ROUTE         1     0.000    R11C12B.FCO to    R11C12C.FCI U1/un1_Count_1_cry_2
FCITOFCO_D  ---     0.162    R11C12C.FCI to    R11C12C.FCO U1/SLICE_206
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI U1/un1_Count_1_cry_4
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO U1/SLICE_205
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI U1/un1_Count_1_cry_6
FCITOF0_DE  ---     0.588    R11C13A.FCI to     R11C13A.F0 U1/SLICE_204
ROUTE         1     0.000     R11C13A.F0 to    R11C13A.DI0 U1/un1_Count_1_s_7_0_S0_0 (to Clk_Count[13])
                  --------
                    6.582   (46.4% logic, 53.6% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C13A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C13A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.590ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[6]  (to Clk_Count[13] +)

   Delay:               6.478ns  (45.5% logic, 54.5% route), 6 logic levels.

 Constraint Details:

      6.478ns physical path delay U1/SLICE_204 to U1/SLICE_205 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 3.590ns

 Physical Path Details:

      Data path U1/SLICE_204 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454    R11C13A.CLK to     R11C13A.Q0 U1/SLICE_204 (from Clk_Count[13])
ROUTE         3     1.538     R11C13A.Q0 to      R7C13D.A1 KEY_NonShake[0]
CTOF_DEL    ---     0.497      R7C13D.A1 to      R7C13D.F1 SLICE_386
ROUTE         1     1.990      R7C13D.F1 to     R11C12A.B0 U1/KEY_NonShake_i[0]
C0TOFCO_DE  ---     1.029     R11C12A.B0 to    R11C12A.FCO U1/SLICE_208
ROUTE         1     0.000    R11C12A.FCO to    R11C12B.FCI U1/un1_Count_1_cry_0
FCITOFCO_D  ---     0.162    R11C12B.FCI to    R11C12B.FCO U1/SLICE_207
ROUTE         1     0.000    R11C12B.FCO to    R11C12C.FCI U1/un1_Count_1_cry_2
FCITOFCO_D  ---     0.162    R11C12C.FCI to    R11C12C.FCO U1/SLICE_206
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI U1/un1_Count_1_cry_4
FCITOF1_DE  ---     0.646    R11C12D.FCI to     R11C12D.F1 U1/SLICE_205
ROUTE         1     0.000     R11C12D.F1 to    R11C12D.DI1 U1/un1_Count_1_cry_5_0_S1_0 (to Clk_Count[13])
                  --------
                    6.478   (45.5% logic, 54.5% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C13A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C12D.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.532ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[5]  (to Clk_Count[13] +)

   Delay:               6.420ns  (45.0% logic, 55.0% route), 6 logic levels.

 Constraint Details:

      6.420ns physical path delay U1/SLICE_204 to U1/SLICE_205 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 3.532ns

 Physical Path Details:

      Data path U1/SLICE_204 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454    R11C13A.CLK to     R11C13A.Q0 U1/SLICE_204 (from Clk_Count[13])
ROUTE         3     1.538     R11C13A.Q0 to      R7C13D.A1 KEY_NonShake[0]
CTOF_DEL    ---     0.497      R7C13D.A1 to      R7C13D.F1 SLICE_386
ROUTE         1     1.990      R7C13D.F1 to     R11C12A.B0 U1/KEY_NonShake_i[0]
C0TOFCO_DE  ---     1.029     R11C12A.B0 to    R11C12A.FCO U1/SLICE_208
ROUTE         1     0.000    R11C12A.FCO to    R11C12B.FCI U1/un1_Count_1_cry_0
FCITOFCO_D  ---     0.162    R11C12B.FCI to    R11C12B.FCO U1/SLICE_207
ROUTE         1     0.000    R11C12B.FCO to    R11C12C.FCI U1/un1_Count_1_cry_2
FCITOFCO_D  ---     0.162    R11C12C.FCI to    R11C12C.FCO U1/SLICE_206
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI U1/un1_Count_1_cry_4
FCITOF0_DE  ---     0.588    R11C12D.FCI to     R11C12D.F0 U1/SLICE_205
ROUTE         1     0.000     R11C12D.F0 to    R11C12D.DI0 U1/un1_Count_1_cry_5_0_S0_0 (to Clk_Count[13])
                  --------
                    6.420   (45.0% logic, 55.0% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C13A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C12D.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.428ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[4]  (to Clk_Count[13] +)

   Delay:               6.316ns  (44.1% logic, 55.9% route), 5 logic levels.

 Constraint Details:

      6.316ns physical path delay U1/SLICE_204 to U1/SLICE_206 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 3.428ns

 Physical Path Details:

      Data path U1/SLICE_204 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454    R11C13A.CLK to     R11C13A.Q0 U1/SLICE_204 (from Clk_Count[13])
ROUTE         3     1.538     R11C13A.Q0 to      R7C13D.A1 KEY_NonShake[0]
CTOF_DEL    ---     0.497      R7C13D.A1 to      R7C13D.F1 SLICE_386
ROUTE         1     1.990      R7C13D.F1 to     R11C12A.B0 U1/KEY_NonShake_i[0]
C0TOFCO_DE  ---     1.029     R11C12A.B0 to    R11C12A.FCO U1/SLICE_208
ROUTE         1     0.000    R11C12A.FCO to    R11C12B.FCI U1/un1_Count_1_cry_0
FCITOFCO_D  ---     0.162    R11C12B.FCI to    R11C12B.FCO U1/SLICE_207
ROUTE         1     0.000    R11C12B.FCO to    R11C12C.FCI U1/un1_Count_1_cry_2
FCITOF1_DE  ---     0.646    R11C12C.FCI to     R11C12C.F1 U1/SLICE_206
ROUTE         1     0.000     R11C12C.F1 to    R11C12C.DI1 U1/un1_Count_1_cry_3_0_S1_0 (to Clk_Count[13])
                  --------
                    6.316   (44.1% logic, 55.9% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C13A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C12C.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[3]  (to Clk_Count[13] +)

   Delay:               6.258ns  (43.6% logic, 56.4% route), 5 logic levels.

 Constraint Details:

      6.258ns physical path delay U1/SLICE_204 to U1/SLICE_206 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 3.370ns

 Physical Path Details:

      Data path U1/SLICE_204 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454    R11C13A.CLK to     R11C13A.Q0 U1/SLICE_204 (from Clk_Count[13])
ROUTE         3     1.538     R11C13A.Q0 to      R7C13D.A1 KEY_NonShake[0]
CTOF_DEL    ---     0.497      R7C13D.A1 to      R7C13D.F1 SLICE_386
ROUTE         1     1.990      R7C13D.F1 to     R11C12A.B0 U1/KEY_NonShake_i[0]
C0TOFCO_DE  ---     1.029     R11C12A.B0 to    R11C12A.FCO U1/SLICE_208
ROUTE         1     0.000    R11C12A.FCO to    R11C12B.FCI U1/un1_Count_1_cry_0
FCITOFCO_D  ---     0.162    R11C12B.FCI to    R11C12B.FCO U1/SLICE_207
ROUTE         1     0.000    R11C12B.FCO to    R11C12C.FCI U1/un1_Count_1_cry_2
FCITOF0_DE  ---     0.588    R11C12C.FCI to     R11C12C.F0 U1/SLICE_206
ROUTE         1     0.000     R11C12C.F0 to    R11C12C.DI0 U1/un1_Count_1_cry_3_0_S0_0 (to Clk_Count[13])
                  --------
                    6.258   (43.6% logic, 56.4% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C13A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C12C.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.266ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[2]  (to Clk_Count[13] +)

   Delay:               6.154ns  (42.7% logic, 57.3% route), 4 logic levels.

 Constraint Details:

      6.154ns physical path delay U1/SLICE_204 to U1/SLICE_207 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 3.266ns

 Physical Path Details:

      Data path U1/SLICE_204 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454    R11C13A.CLK to     R11C13A.Q0 U1/SLICE_204 (from Clk_Count[13])
ROUTE         3     1.538     R11C13A.Q0 to      R7C13D.A1 KEY_NonShake[0]
CTOF_DEL    ---     0.497      R7C13D.A1 to      R7C13D.F1 SLICE_386
ROUTE         1     1.990      R7C13D.F1 to     R11C12A.B0 U1/KEY_NonShake_i[0]
C0TOFCO_DE  ---     1.029     R11C12A.B0 to    R11C12A.FCO U1/SLICE_208
ROUTE         1     0.000    R11C12A.FCO to    R11C12B.FCI U1/un1_Count_1_cry_0
FCITOF1_DE  ---     0.646    R11C12B.FCI to     R11C12B.F1 U1/SLICE_207
ROUTE         1     0.000     R11C12B.F1 to    R11C12B.DI1 U1/un1_Count_1_cry_1_0_S1_0 (to Clk_Count[13])
                  --------
                    6.154   (42.7% logic, 57.3% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C13A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C12B.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 3.208ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[1]  (to Clk_Count[13] +)

   Delay:               6.096ns  (42.1% logic, 57.9% route), 4 logic levels.

 Constraint Details:

      6.096ns physical path delay U1/SLICE_204 to U1/SLICE_207 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 3.208ns

 Physical Path Details:

      Data path U1/SLICE_204 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454    R11C13A.CLK to     R11C13A.Q0 U1/SLICE_204 (from Clk_Count[13])
ROUTE         3     1.538     R11C13A.Q0 to      R7C13D.A1 KEY_NonShake[0]
CTOF_DEL    ---     0.497      R7C13D.A1 to      R7C13D.F1 SLICE_386
ROUTE         1     1.990      R7C13D.F1 to     R11C12A.B0 U1/KEY_NonShake_i[0]
C0TOFCO_DE  ---     1.029     R11C12A.B0 to    R11C12A.FCO U1/SLICE_208
ROUTE         1     0.000    R11C12A.FCO to    R11C12B.FCI U1/un1_Count_1_cry_0
FCITOF0_DE  ---     0.588    R11C12B.FCI to     R11C12B.F0 U1/SLICE_207
ROUTE         1     0.000     R11C12B.F0 to    R11C12B.DI0 U1/un1_Count_1_cry_1_0_S0_0 (to Clk_Count[13])
                  --------
                    6.096   (42.1% logic, 57.9% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_204:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C13A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to    R11C12B.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.960ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U2/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U2/Count[7]  (to Clk_Count[13] +)

   Delay:               5.848ns  (52.2% logic, 47.8% route), 7 logic levels.

 Constraint Details:

      5.848ns physical path delay U2/SLICE_199 to U2/SLICE_199 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 2.960ns

 Physical Path Details:

      Data path U2/SLICE_199 to U2/SLICE_199:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R7C16A.CLK to      R7C16A.Q0 U2/SLICE_199 (from Clk_Count[13])
ROUTE         3     1.365      R7C16A.Q0 to      R7C13D.B0 KEY_NonShake[1]
CTOF_DEL    ---     0.497      R7C13D.B0 to      R7C13D.F0 SLICE_386
ROUTE         1     1.429      R7C13D.F0 to      R7C15A.B0 U2/KEY_NonShake_i[1]
C0TOFCO_DE  ---     1.029      R7C15A.B0 to     R7C15A.FCO U2/SLICE_203
ROUTE         1     0.000     R7C15A.FCO to     R7C15B.FCI U2/un1_Count_1_cry_0
FCITOFCO_D  ---     0.162     R7C15B.FCI to     R7C15B.FCO U2/SLICE_202
ROUTE         1     0.000     R7C15B.FCO to     R7C15C.FCI U2/un1_Count_1_cry_2
FCITOFCO_D  ---     0.162     R7C15C.FCI to     R7C15C.FCO U2/SLICE_201
ROUTE         1     0.000     R7C15C.FCO to     R7C15D.FCI U2/un1_Count_1_cry_4
FCITOFCO_D  ---     0.162     R7C15D.FCI to     R7C15D.FCO U2/SLICE_200
ROUTE         1     0.000     R7C15D.FCO to     R7C16A.FCI U2/un1_Count_1_cry_6
FCITOF0_DE  ---     0.588     R7C16A.FCI to      R7C16A.F0 U2/SLICE_199
ROUTE         1     0.000      R7C16A.F0 to     R7C16A.DI0 U2/un1_Count_1_s_7_0_S0 (to Clk_Count[13])
                  --------
                    5.848   (52.2% logic, 47.8% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U2/SLICE_199:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to     R7C16A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U2/SLICE_199:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to     R7C16A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.856ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U2/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U2/Count[6]  (to Clk_Count[13] +)

   Delay:               5.744ns  (51.4% logic, 48.6% route), 6 logic levels.

 Constraint Details:

      5.744ns physical path delay U2/SLICE_199 to U2/SLICE_200 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 2.856ns

 Physical Path Details:

      Data path U2/SLICE_199 to U2/SLICE_200:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R7C16A.CLK to      R7C16A.Q0 U2/SLICE_199 (from Clk_Count[13])
ROUTE         3     1.365      R7C16A.Q0 to      R7C13D.B0 KEY_NonShake[1]
CTOF_DEL    ---     0.497      R7C13D.B0 to      R7C13D.F0 SLICE_386
ROUTE         1     1.429      R7C13D.F0 to      R7C15A.B0 U2/KEY_NonShake_i[1]
C0TOFCO_DE  ---     1.029      R7C15A.B0 to     R7C15A.FCO U2/SLICE_203
ROUTE         1     0.000     R7C15A.FCO to     R7C15B.FCI U2/un1_Count_1_cry_0
FCITOFCO_D  ---     0.162     R7C15B.FCI to     R7C15B.FCO U2/SLICE_202
ROUTE         1     0.000     R7C15B.FCO to     R7C15C.FCI U2/un1_Count_1_cry_2
FCITOFCO_D  ---     0.162     R7C15C.FCI to     R7C15C.FCO U2/SLICE_201
ROUTE         1     0.000     R7C15C.FCO to     R7C15D.FCI U2/un1_Count_1_cry_4
FCITOF1_DE  ---     0.646     R7C15D.FCI to      R7C15D.F1 U2/SLICE_200
ROUTE         1     0.000      R7C15D.F1 to     R7C15D.DI1 U2/un1_Count_1_cry_5_0_S1 (to Clk_Count[13])
                  --------
                    5.744   (51.4% logic, 48.6% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U2/SLICE_199:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to     R7C16A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U2/SLICE_200:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to     R7C15D.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.


Error: The following path exceeds requirements by 2.798ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U2/Count[7]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U2/Count[5]  (to Clk_Count[13] +)

   Delay:               5.686ns  (50.9% logic, 49.1% route), 6 logic levels.

 Constraint Details:

      5.686ns physical path delay U2/SLICE_199 to U2/SLICE_200 exceeds
      3.054ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.888ns) by 2.798ns

 Physical Path Details:

      Data path U2/SLICE_199 to U2/SLICE_200:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R7C16A.CLK to      R7C16A.Q0 U2/SLICE_199 (from Clk_Count[13])
ROUTE         3     1.365      R7C16A.Q0 to      R7C13D.B0 KEY_NonShake[1]
CTOF_DEL    ---     0.497      R7C13D.B0 to      R7C13D.F0 SLICE_386
ROUTE         1     1.429      R7C13D.F0 to      R7C15A.B0 U2/KEY_NonShake_i[1]
C0TOFCO_DE  ---     1.029      R7C15A.B0 to     R7C15A.FCO U2/SLICE_203
ROUTE         1     0.000     R7C15A.FCO to     R7C15B.FCI U2/un1_Count_1_cry_0
FCITOFCO_D  ---     0.162     R7C15B.FCI to     R7C15B.FCO U2/SLICE_202
ROUTE         1     0.000     R7C15B.FCO to     R7C15C.FCI U2/un1_Count_1_cry_2
FCITOFCO_D  ---     0.162     R7C15C.FCI to     R7C15C.FCO U2/SLICE_201
ROUTE         1     0.000     R7C15C.FCO to     R7C15D.FCI U2/un1_Count_1_cry_4
FCITOF0_DE  ---     0.588     R7C15D.FCI to      R7C15D.F0 U2/SLICE_200
ROUTE         1     0.000      R7C15D.F0 to     R7C15D.DI0 U2/un1_Count_1_cry_5_0_S0 (to Clk_Count[13])
                  --------
                    5.686   (50.9% logic, 49.1% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U2/SLICE_199:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to     R7C16A.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U2/SLICE_200:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     4.998       R9C3D.Q0 to     R7C15D.CLK Clk_Count[13]
                  --------
                    4.998   (0.0% logic, 100.0% route), 0 logic levels.

Warning: 148.192MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "FSMC_NADV_c" 399.840000 MHz ;
            16 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 0.001ns
         The internal maximum frequency of the following component is 400.000 MHz

 Logical Details:  Cell type  Pin name       Component name

   Destination:    SLICE      CLK            SLICE_264

   Delay:               2.500ns -- based on Minimum Pulse Width


Passed: The following path meets requirements by 0.367ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[6]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[6]  (to FSMC_NADV_c +)

   Delay:               1.968ns  (48.3% logic, 51.7% route), 2 logic levels.

 Constraint Details:

      1.968ns physical path delay SLICE_267 to SLICE_267 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.367ns

 Physical Path Details:

      Data path SLICE_267 to SLICE_267:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R9C8B.CLK to       R9C8B.Q0 SLICE_267 (from FSMC_NADV_c)
ROUTE         2     1.017       R9C8B.Q0 to       R9C8B.B0 FSMC_Add[6]
CTOF_DEL    ---     0.497       R9C8B.B0 to       R9C8B.F0 SLICE_267
ROUTE         1     0.000       R9C8B.F0 to      R9C8B.DI0 FSMC_Add_0[6] (to FSMC_NADV_c)
                  --------
                    1.968   (48.3% logic, 51.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_267:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R9C8B.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_267:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R9C8B.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.687ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[0]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[0]  (to FSMC_NADV_c +)

   Delay:               1.648ns  (57.7% logic, 42.3% route), 2 logic levels.

 Constraint Details:

      1.648ns physical path delay SLICE_264 to SLICE_264 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.687ns

 Physical Path Details:

      Data path SLICE_264 to SLICE_264:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R6C8C.CLK to       R6C8C.Q0 SLICE_264 (from FSMC_NADV_c)
ROUTE        43     0.697       R6C8C.Q0 to       R6C8C.A0 FSMC_Add[0]
CTOF_DEL    ---     0.497       R6C8C.A0 to       R6C8C.F0 SLICE_264
ROUTE         1     0.000       R6C8C.F0 to      R6C8C.DI0 FSMC_Add_0[0] (to FSMC_NADV_c)
                  --------
                    1.648   (57.7% logic, 42.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_264:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R6C8C.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_264:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R6C8C.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.693ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[1]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[1]  (to FSMC_NADV_c +)

   Delay:               1.642ns  (57.9% logic, 42.1% route), 2 logic levels.

 Constraint Details:

      1.642ns physical path delay SLICE_264 to SLICE_264 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.693ns

 Physical Path Details:

      Data path SLICE_264 to SLICE_264:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R6C8C.CLK to       R6C8C.Q1 SLICE_264 (from FSMC_NADV_c)
ROUTE        43     0.691       R6C8C.Q1 to       R6C8C.A1 FSMC_Add[1]
CTOF_DEL    ---     0.497       R6C8C.A1 to       R6C8C.F1 SLICE_264
ROUTE         1     0.000       R6C8C.F1 to      R6C8C.DI1 FSMC_Add_0[1] (to FSMC_NADV_c)
                  --------
                    1.642   (57.9% logic, 42.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_264:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R6C8C.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_264:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R6C8C.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.693ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[3]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[3]  (to FSMC_NADV_c +)

   Delay:               1.642ns  (57.9% logic, 42.1% route), 2 logic levels.

 Constraint Details:

      1.642ns physical path delay SLICE_265 to SLICE_265 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.693ns

 Physical Path Details:

      Data path SLICE_265 to SLICE_265:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R10C8D.CLK to      R10C8D.Q1 SLICE_265 (from FSMC_NADV_c)
ROUTE        18     0.691      R10C8D.Q1 to      R10C8D.A1 FSMC_Add[3]
CTOF_DEL    ---     0.497      R10C8D.A1 to      R10C8D.F1 SLICE_265
ROUTE         1     0.000      R10C8D.F1 to     R10C8D.DI1 FSMC_Add_0[3] (to FSMC_NADV_c)
                  --------
                    1.642   (57.9% logic, 42.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_265:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to     R10C8D.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_265:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to     R10C8D.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.711ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[2]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[2]  (to FSMC_NADV_c +)

   Delay:               1.624ns  (58.6% logic, 41.4% route), 2 logic levels.

 Constraint Details:

      1.624ns physical path delay SLICE_265 to SLICE_265 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.711ns

 Physical Path Details:

      Data path SLICE_265 to SLICE_265:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R10C8D.CLK to      R10C8D.Q0 SLICE_265 (from FSMC_NADV_c)
ROUTE        43     0.673      R10C8D.Q0 to      R10C8D.A0 FSMC_Add[2]
CTOF_DEL    ---     0.497      R10C8D.A0 to      R10C8D.F0 SLICE_265
ROUTE         1     0.000      R10C8D.F0 to     R10C8D.DI0 FSMC_Add_0[2] (to FSMC_NADV_c)
                  --------
                    1.624   (58.6% logic, 41.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_265:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to     R10C8D.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_265:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to     R10C8D.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.717ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[4]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[4]  (to FSMC_NADV_c +)

   Delay:               1.618ns  (58.8% logic, 41.2% route), 2 logic levels.

 Constraint Details:

      1.618ns physical path delay SLICE_266 to SLICE_266 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.717ns

 Physical Path Details:

      Data path SLICE_266 to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R9C7A.CLK to       R9C7A.Q0 SLICE_266 (from FSMC_NADV_c)
ROUTE         2     0.667       R9C7A.Q0 to       R9C7A.A0 FSMC_Add[4]
CTOF_DEL    ---     0.497       R9C7A.A0 to       R9C7A.F0 SLICE_266
ROUTE         1     0.000       R9C7A.F0 to      R9C7A.DI0 FSMC_Add_0[4] (to FSMC_NADV_c)
                  --------
                    1.618   (58.8% logic, 41.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R9C7A.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R9C7A.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.717ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[5]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[5]  (to FSMC_NADV_c +)

   Delay:               1.618ns  (58.8% logic, 41.2% route), 2 logic levels.

 Constraint Details:

      1.618ns physical path delay SLICE_266 to SLICE_266 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.717ns

 Physical Path Details:

      Data path SLICE_266 to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454      R9C7A.CLK to       R9C7A.Q1 SLICE_266 (from FSMC_NADV_c)
ROUTE         2     0.667       R9C7A.Q1 to       R9C7A.A1 FSMC_Add[5]
CTOF_DEL    ---     0.497       R9C7A.A1 to       R9C7A.F1 SLICE_266
ROUTE         1     0.000       R9C7A.F1 to      R9C7A.DI1 FSMC_Add_0[5] (to FSMC_NADV_c)
                  --------
                    1.618   (58.8% logic, 41.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R9C7A.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to      R9C7A.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.717ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[9]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[9]  (to FSMC_NADV_c +)

   Delay:               1.618ns  (58.8% logic, 41.2% route), 2 logic levels.

 Constraint Details:

      1.618ns physical path delay SLICE_268 to SLICE_268 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.717ns

 Physical Path Details:

      Data path SLICE_268 to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R10C7D.CLK to      R10C7D.Q1 SLICE_268 (from FSMC_NADV_c)
ROUTE         2     0.667      R10C7D.Q1 to      R10C7D.A1 FSMC_Add[9]
CTOF_DEL    ---     0.497      R10C7D.A1 to      R10C7D.F1 SLICE_268
ROUTE         1     0.000      R10C7D.F1 to     R10C7D.DI1 FSMC_Add_0[9] (to FSMC_NADV_c)
                  --------
                    1.618   (58.8% logic, 41.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.219        1.PADDI to     R10C7D.CLK FSMC_NADV_c
                  --------
                    4.219   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.219        1.PADDI to     R10C7D.CLK FSMC_NADV_c
                  --------
                    4.219   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.717ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[8]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[8]  (to FSMC_NADV_c +)

   Delay:               1.618ns  (58.8% logic, 41.2% route), 2 logic levels.

 Constraint Details:

      1.618ns physical path delay SLICE_268 to SLICE_268 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.717ns

 Physical Path Details:

      Data path SLICE_268 to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R10C7D.CLK to      R10C7D.Q0 SLICE_268 (from FSMC_NADV_c)
ROUTE         2     0.667      R10C7D.Q0 to      R10C7D.A0 FSMC_Add[8]
CTOF_DEL    ---     0.497      R10C7D.A0 to      R10C7D.F0 SLICE_268
ROUTE         1     0.000      R10C7D.F0 to     R10C7D.DI0 FSMC_Add_0[8] (to FSMC_NADV_c)
                  --------
                    1.618   (58.8% logic, 41.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.219        1.PADDI to     R10C7D.CLK FSMC_NADV_c
                  --------
                    4.219   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.219        1.PADDI to     R10C7D.CLK FSMC_NADV_c
                  --------
                    4.219   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.717ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[10]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[10]  (to FSMC_NADV_c +)

   Delay:               1.618ns  (58.8% logic, 41.2% route), 2 logic levels.

 Constraint Details:

      1.618ns physical path delay SLICE_269 to SLICE_269 meets
      2.501ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 2.335ns) by 0.717ns

 Physical Path Details:

      Data path SLICE_269 to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.454     R10C6B.CLK to      R10C6B.Q0 SLICE_269 (from FSMC_NADV_c)
ROUTE         2     0.667      R10C6B.Q0 to      R10C6B.A0 FSMC_Add[10]
CTOF_DEL    ---     0.497      R10C6B.A0 to      R10C6B.F0 SLICE_269
ROUTE         1     0.000      R10C6B.F0 to     R10C6B.DI0 FSMC_Add_0[10] (to FSMC_NADV_c)
                  --------
                    1.618   (58.8% logic, 41.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to     R10C6B.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     4.204        1.PADDI to     R10C6B.CLK FSMC_NADV_c
                  --------
                    4.204   (0.0% logic, 100.0% route), 0 logic levels.

Report:  400.000MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "Clk_c" 269.469000 MHz ;  |  269.469 MHz|    2.660 MHz|   3 *
                                        |             |             |
FREQUENCY NET "Clk_Count[16]"           |             |             |
399.840000 MHz ;                        |  399.840 MHz|    7.644 MHz|   5 *
                                        |             |             |
FREQUENCY NET "un3_tb_pluse_q2_buf"     |             |             |
399.840000 MHz ;                        |  399.840 MHz|   50.446 MHz|   1 *
                                        |             |             |
FREQUENCY NET "U3/Clk_10ms[17]"         |             |             |
335.909000 MHz ;                        |  335.909 MHz|  157.109 MHz|   7 *
                                        |             |             |
FREQUENCY NET "LaserPulse_Sig"          |             |             |
319.693000 MHz ;                        |  319.693 MHz|  166.694 MHz|  10 *
                                        |             |             |
FREQUENCY NET "Clk_Count[13]"           |             |             |
327.439000 MHz ;                        |  327.439 MHz|  148.192 MHz|   7 *
                                        |             |             |
FREQUENCY NET "FSMC_NADV_c" 399.840000  |             |             |
MHz ;                                   |  399.840 MHz|  400.000 MHz|   0  
                                        |             |             |
----------------------------------------------------------------------------


6 preferences(marked by "*" above) not met.

----------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
----------------------------------------------------------------------------
U5/un11_count_cry_14                    |       1|    1146|     25.43%
                                        |        |        |
U6/un11_count_cry_14                    |       1|     990|     21.97%
                                        |        |        |
U5/un11_count_cry_18                    |       1|     977|     21.68%
                                        |        |        |
U8/un11_count_cry_14                    |       1|     957|     21.24%
                                        |        |        |
U5/un11_count_cry_16                    |       1|     950|     21.08%
                                        |        |        |
U5/un11_count_cry_20                    |       1|     943|     20.93%
                                        |        |        |
U5/un11_count_cry_22                    |       1|     901|     20.00%
                                        |        |        |
U6/un11_count_cry_18                    |       1|     893|     19.82%
                                        |        |        |
U5/un11_count_cry_12                    |       1|     890|     19.75%
                                        |        |        |
U6/un11_count_cry_16                    |       1|     878|     19.49%
                                        |        |        |
U6/un11_count_cry_20                    |       1|     855|     18.97%
                                        |        |        |
U8/un11_count_cry_18                    |       1|     846|     18.77%
                                        |        |        |
U8/un11_count_cry_16                    |       1|     845|     18.75%
                                        |        |        |
U5/un11_count_cry_24                    |       1|     841|     18.66%
                                        |        |        |
U6/un11_count_cry_22                    |       1|     817|     18.13%
                                        |        |        |
U6/un9_count_0_cry_4                    |       1|     802|     17.80%
                                        |        |        |
U6/un11_count_cry_12                    |       1|     796|     17.67%
                                        |        |        |
U8/un11_count_cry_20                    |       1|     793|     17.60%
                                        |        |        |
U6/un9_count_0_cry_2                    |       1|     779|     17.29%
                                        |        |        |
U8/un11_count_cry_12                    |       1|     762|     16.91%
                                        |        |        |
U5/un11_count_cry_26                    |       1|     761|     16.89%
                                        |        |        |
U6/un11_count_cry_24                    |       1|     738|     16.38%
                                        |        |        |
U8/un11_count_cry_22                    |       1|     722|     16.02%
                                        |        |        |
U5/un9_count_0_cry_4                    |       1|     695|     15.42%
                                        |        |        |
U5/un11_count_cry_10                    |       1|     679|     15.07%
                                        |        |        |
U8/un9_count_0_cry_6                    |       1|     675|     14.98%
                                        |        |        |
U6/un9_count_0_cry_6                    |       1|     655|     14.54%
                                        |        |        |
U5/un9_count_0_cry_6                    |       1|     649|     14.40%
                                        |        |        |
U5/un9_count_0_cry_2                    |       1|     645|     14.31%
                                        |        |        |
U8/un9_count_0_cry_4                    |       1|     640|     14.20%
                                        |        |        |
U8/un11_count_cry_24                    |       1|     639|     14.18%
                                        |        |        |
U6/un11_count_cry_26                    |       1|     631|     14.00%
                                        |        |        |
U5/un11_count_cry_28                    |       1|     622|     13.80%
                                        |        |        |
U5/un9_count_0_cry_8                    |       1|     621|     13.78%
                                        |        |        |
U3/count                                |      29|     609|     13.52%
                                        |        |        |
U6/un11_count_cry_10                    |       1|     606|     13.45%
                                        |        |        |
U3/count_cry_22                         |       1|     585|     12.98%
                                        |        |        |
U6/un9_count_0                          |       6|     579|     12.85%
                                        |        |        |
U8/un9_count_0_cry_8                    |       1|     579|     12.85%
                                        |        |        |
U3/un2_count_i                          |      12|     576|     12.78%
                                        |        |        |
U8/un11_count_cry_10                    |       1|     571|     12.67%
                                        |        |        |
U6/un9_count_0_cry_8                    |       1|     564|     12.52%
                                        |        |        |
U8/un11_count_cry_26                    |       1|     545|     12.09%
                                        |        |        |
U3/count_cry_20                         |       1|     537|     11.92%
                                        |        |        |
U8/un9_count_0                          |       5|     525|     11.65%
                                        |        |        |
U8/un9_count_0_cry_2                    |       1|     498|     11.05%
                                        |        |        |
U6/un11_count_cry_28                    |       1|     495|     10.99%
                                        |        |        |
U5/un11_count_cry_8                     |       1|     489|     10.85%
                                        |        |        |
U3/count_cry_18                         |       1|     489|     10.85%
                                        |        |        |
U5/un9_count_0_cry_10                   |       1|     487|     10.81%
                                        |        |        |
U6/un11_count_cry_8                     |       1|     461|     10.23%
                                        |        |        |
----------------------------------------------------------------------------


Clock Domains Analysis
------------------------

Found 8 clocks:

Clock Domain: un3_tb_pluse_q2_buf   Source: SLICE_338.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: Clk_c   Source: Clk.PAD
      Covered under: FREQUENCY NET "un3_tb_pluse_q2_buf" 399.840000 MHz ;   Transfers: 1

Clock Domain: U3/Clk_10ms[17]   Source: U3/SLICE_45.Q0   Loads: 8
   Covered under: FREQUENCY NET "U3/Clk_10ms[17]" 335.909000 MHz ;

   Data transfers from:
   Clock Domain: FSMC_NWE_c   Source: FSMC_NWE.PAD
      Not reported because source and destination domains are unrelated.

Clock Domain: LaserPulse_Sig   Source: SLICE_390.F0   Loads: 11
   Covered under: FREQUENCY NET "LaserPulse_Sig" 319.693000 MHz ;

   Data transfers from:
   Clock Domain: FSMC_NWE_c   Source: FSMC_NWE.PAD
      Not reported because source and destination domains are unrelated.

Clock Domain: FSMC_NWE_c   Source: FSMC_NWE.PAD   Loads: 74
   No transfer within this clock domain is found

Clock Domain: FSMC_NADV_c   Source: FSMC_NADV.PAD   Loads: 8
   Covered under: FREQUENCY NET "FSMC_NADV_c" 399.840000 MHz ;

Clock Domain: Clk_c   Source: Clk.PAD   Loads: 138
   Covered under: FREQUENCY NET "Clk_c" 269.469000 MHz ;

   Data transfers from:
   Clock Domain: U3/Clk_10ms[17]   Source: U3/SLICE_45.Q0
      Covered under: FREQUENCY NET "Clk_c" 269.469000 MHz ;   Transfers: 1

   Clock Domain: LaserPulse_Sig   Source: SLICE_390.F0
      Covered under: FREQUENCY NET "Clk_c" 269.469000 MHz ;   Transfers: 1

   Clock Domain: FSMC_NWE_c   Source: FSMC_NWE.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

   Clock Domain: Clk_Count[16]   Source: SLICE_227.Q1
      Covered under: FREQUENCY NET "Clk_c" 269.469000 MHz ;   Transfers: 1

Clock Domain: Clk_Count[16]   Source: SLICE_227.Q1   Loads: 6
   Covered under: FREQUENCY NET "Clk_Count[16]" 399.840000 MHz ;

   Data transfers from:
   Clock Domain: Clk_c   Source: Clk.PAD
      Covered under: FREQUENCY NET "Clk_Count[16]" 399.840000 MHz ;   Transfers: 1

Clock Domain: Clk_Count[13]   Source: SLICE_228.Q0   Loads: 11
   Covered under: FREQUENCY NET "Clk_Count[13]" 327.439000 MHz ;


Timing summary (Setup):
---------------

Timing errors: 4506  Score: 41478171
Cumulative negative slack: 41478171

Constraints cover 18092 paths, 15 nets, and 1501 connections (65.09% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.14.0.75.2
Tue Nov 19 16:14:09 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2024 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o CL202_MXO2_2000HC.twr -gui -msgset D:/Light_Source/CPLD/CL202_B(I232O232-202107231608)/promote.xml CL202_MXO2_2000HC.ncd CL202_MXO2_2000HC.prf 
Design file:     cl202_mxo2_2000hc.ncd
Preference file: cl202_mxo2_2000hc.prf
Device,speed:    LCMXO2-2000HE,m
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "Clk_c" 269.469000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[0]  (from Clk_c +)
   Destination:    FF         Data in        Clr_Count[0]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_0 to SLICE_0 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_0 to SLICE_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R10C14A.CLK to     R10C14A.Q1 SLICE_0 (from Clk_c)
ROUTE         1     0.127     R10C14A.Q1 to     R10C14A.A1 Clr_Count[0]
CTOF_DEL    ---     0.099     R10C14A.A1 to     R10C14A.F1 SLICE_0
ROUTE         1     0.000     R10C14A.F1 to    R10C14A.DI1 Clr_Count_s[0] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to    R10C14A.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to    R10C14A.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[15]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[15]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_227 to SLICE_227 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_227 to SLICE_227:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C4A.CLK to       R9C4A.Q0 SLICE_227 (from Clk_c)
ROUTE         1     0.127       R9C4A.Q0 to       R9C4A.A0 Clk_Count[15]
CTOF_DEL    ---     0.099       R9C4A.A0 to       R9C4A.F0 SLICE_227
ROUTE         1     0.000       R9C4A.F0 to      R9C4A.DI0 Clk_Count_s[15] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_227:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_227:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[14]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[14]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_228 to SLICE_228 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_228 to SLICE_228:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C3D.CLK to       R9C3D.Q1 SLICE_228 (from Clk_c)
ROUTE         1     0.127       R9C3D.Q1 to       R9C3D.A1 Clk_Count[14]
CTOF_DEL    ---     0.099       R9C3D.A1 to       R9C3D.F1 SLICE_228
ROUTE         1     0.000       R9C3D.F1 to      R9C3D.DI1 Clk_Count_s[14] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_228:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3D.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_228:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3D.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[11]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[11]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_229 to SLICE_229 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_229 to SLICE_229:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C3C.CLK to       R9C3C.Q0 SLICE_229 (from Clk_c)
ROUTE         1     0.127       R9C3C.Q0 to       R9C3C.A0 Clk_Count[11]
CTOF_DEL    ---     0.099       R9C3C.A0 to       R9C3C.F0 SLICE_229
ROUTE         1     0.000       R9C3C.F0 to      R9C3C.DI0 Clk_Count_s[11] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_229:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3C.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_229:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3C.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[12]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[12]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_229 to SLICE_229 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_229 to SLICE_229:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C3C.CLK to       R9C3C.Q1 SLICE_229 (from Clk_c)
ROUTE         1     0.127       R9C3C.Q1 to       R9C3C.A1 Clk_Count[12]
CTOF_DEL    ---     0.099       R9C3C.A1 to       R9C3C.F1 SLICE_229
ROUTE         1     0.000       R9C3C.F1 to      R9C3C.DI1 Clk_Count_s[12] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_229:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3C.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_229:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3C.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[9]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[9]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_230 to SLICE_230 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_230 to SLICE_230:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C3B.CLK to       R9C3B.Q0 SLICE_230 (from Clk_c)
ROUTE         1     0.127       R9C3B.Q0 to       R9C3B.A0 Clk_Count[9]
CTOF_DEL    ---     0.099       R9C3B.A0 to       R9C3B.F0 SLICE_230
ROUTE         1     0.000       R9C3B.F0 to      R9C3B.DI0 Clk_Count_s[9] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_230:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3B.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_230:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3B.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[10]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[10]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_230 to SLICE_230 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_230 to SLICE_230:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C3B.CLK to       R9C3B.Q1 SLICE_230 (from Clk_c)
ROUTE         1     0.127       R9C3B.Q1 to       R9C3B.A1 Clk_Count[10]
CTOF_DEL    ---     0.099       R9C3B.A1 to       R9C3B.F1 SLICE_230
ROUTE         1     0.000       R9C3B.F1 to      R9C3B.DI1 Clk_Count_s[10] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_230:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3B.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_230:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3B.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[8]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[8]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_231 to SLICE_231 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_231 to SLICE_231:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C3A.CLK to       R9C3A.Q1 SLICE_231 (from Clk_c)
ROUTE         1     0.127       R9C3A.Q1 to       R9C3A.A1 Clk_Count[8]
CTOF_DEL    ---     0.099       R9C3A.A1 to       R9C3A.F1 SLICE_231
ROUTE         1     0.000       R9C3A.F1 to      R9C3A.DI1 Clk_Count_s[8] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_231:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3A.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_231:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3A.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[7]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[7]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_231 to SLICE_231 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_231 to SLICE_231:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C3A.CLK to       R9C3A.Q0 SLICE_231 (from Clk_c)
ROUTE         1     0.127       R9C3A.Q0 to       R9C3A.A0 Clk_Count[7]
CTOF_DEL    ---     0.099       R9C3A.A0 to       R9C3A.F0 SLICE_231
ROUTE         1     0.000       R9C3A.F0 to      R9C3A.DI0 Clk_Count_s[7] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_231:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3A.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_231:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.511       31.PADDI to      R9C3A.CLK Clk_c
                  --------
                    1.511   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clk_Count[5]  (from Clk_c +)
   Destination:    FF         Data in        Clk_Count[5]  (to Clk_c +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay SLICE_232 to SLICE_232 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path SLICE_232 to SLICE_232:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C2D.CLK to       R9C2D.Q0 SLICE_232 (from Clk_c)
ROUTE         1     0.127       R9C2D.Q0 to       R9C2D.A0 Clk_Count[5]
CTOF_DEL    ---     0.099       R9C2D.A0 to       R9C2D.F0 SLICE_232
ROUTE         1     0.000       R9C2D.F0 to      R9C2D.DI0 Clk_Count_s[5] (to Clk_c)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_232:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.510       31.PADDI to      R9C2D.CLK Clk_c
                  --------
                    1.510   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clk to SLICE_232:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       138     1.510       31.PADDI to      R9C2D.CLK Clk_c
                  --------
                    1.510   (0.0% logic, 100.0% route), 0 logic levels.


================================================================================
Preference: FREQUENCY NET "Clk_Count[16]" 399.840000 MHz ;
            109 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.211ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[8]  (to Clk_Count[16] +)

   Delay:               1.162ns  (19.8% logic, 80.2% route), 2 logic levels.

 Constraint Details:

      1.162ns physical path delay SLICE_277 to SLICE_236 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.964ns skew requirement (totaling 0.951ns) by 0.211ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_236:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.932      R9C15C.Q0 to      R9C15A.A1 TB_watchdog
CTOF_DEL    ---     0.099      R9C15A.A1 to      R9C15A.F1 SLICE_236
ROUTE         1     0.000      R9C15A.F1 to     R9C15A.DI1 TB_watchdog_s[8] (to Clk_Count[16])
                  --------
                    1.162   (19.8% logic, 80.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_236:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.813       R9C4A.Q1 to     R9C15A.CLK Clk_Count[16]
                  --------
                    2.884   (19.4% logic, 80.6% route), 2 logic levels.


Passed: The following path meets requirements by 0.211ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[7]  (to Clk_Count[16] +)

   Delay:               1.162ns  (19.8% logic, 80.2% route), 2 logic levels.

 Constraint Details:

      1.162ns physical path delay SLICE_277 to SLICE_236 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.964ns skew requirement (totaling 0.951ns) by 0.211ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_236:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.932      R9C15C.Q0 to      R9C15A.A0 TB_watchdog
CTOF_DEL    ---     0.099      R9C15A.A0 to      R9C15A.F0 SLICE_236
ROUTE         1     0.000      R9C15A.F0 to     R9C15A.DI0 TB_watchdog_s[7] (to Clk_Count[16])
                  --------
                    1.162   (19.8% logic, 80.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_236:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.813       R9C4A.Q1 to     R9C15A.CLK Clk_Count[16]
                  --------
                    2.884   (19.4% logic, 80.6% route), 2 logic levels.


Passed: The following path meets requirements by 0.333ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[8]  (to Clk_Count[16] +)

   Delay:               1.284ns  (27.4% logic, 72.6% route), 2 logic levels.

 Constraint Details:

      1.284ns physical path delay SLICE_277 to SLICE_236 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.964ns skew requirement (totaling 0.951ns) by 0.333ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_236:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.932      R9C15C.Q0 to      R9C15A.A0 TB_watchdog
CTOF1_DEL   ---     0.221      R9C15A.A0 to      R9C15A.F1 SLICE_236
ROUTE         1     0.000      R9C15A.F1 to     R9C15A.DI1 TB_watchdog_s[8] (to Clk_Count[16])
                  --------
                    1.284   (27.4% logic, 72.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_236:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.813       R9C4A.Q1 to     R9C15A.CLK Clk_Count[16]
                  --------
                    2.884   (19.4% logic, 80.6% route), 2 logic levels.


Passed: The following path meets requirements by 0.364ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[8]  (to Clk_Count[16] +)
                   FF                        TB_watchdog[7]

   Delay:               1.304ns  (17.6% logic, 82.4% route), 2 logic levels.

 Constraint Details:

      1.304ns physical path delay SLICE_277 to SLICE_236 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.024ns CE_HLD and
      0.000ns delay constraint less
     -0.964ns skew requirement (totaling 0.940ns) by 0.364ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_236:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.932      R9C15C.Q0 to      R9C15C.A1 TB_watchdog
CTOF_DEL    ---     0.099      R9C15C.A1 to      R9C15C.F1 SLICE_277
ROUTE         5     0.142      R9C15C.F1 to      R9C15A.CE TB_watchdoge (to Clk_Count[16])
                  --------
                    1.304   (17.6% logic, 82.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_236:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.813       R9C4A.Q1 to     R9C15A.CLK Clk_Count[16]
                  --------
                    2.884   (19.4% logic, 80.6% route), 2 logic levels.


Passed: The following path meets requirements by 0.402ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[5]  (to Clk_Count[16] +)

   Delay:               1.153ns  (19.9% logic, 80.1% route), 2 logic levels.

 Constraint Details:

      1.153ns physical path delay SLICE_277 to SLICE_237 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.764ns skew requirement (totaling 0.751ns) by 0.402ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.923      R9C15C.Q0 to      R9C14D.A0 TB_watchdog
CTOF_DEL    ---     0.099      R9C14D.A0 to      R9C14D.F0 SLICE_237
ROUTE         1     0.000      R9C14D.F0 to     R9C14D.DI0 TB_watchdog_s[5] (to Clk_Count[16])
                  --------
                    1.153   (19.9% logic, 80.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.613       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    2.684   (20.9% logic, 79.1% route), 2 logic levels.


Passed: The following path meets requirements by 0.411ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[2]  (to Clk_Count[16] +)

   Delay:               1.162ns  (19.8% logic, 80.2% route), 2 logic levels.

 Constraint Details:

      1.162ns physical path delay SLICE_277 to SLICE_239 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.764ns skew requirement (totaling 0.751ns) by 0.411ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_239:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.932      R9C15C.Q0 to      R9C14B.A1 TB_watchdog
CTOF_DEL    ---     0.099      R9C14B.A1 to      R9C14B.F1 SLICE_239
ROUTE         1     0.000      R9C14B.F1 to     R9C14B.DI1 TB_watchdog_s[2] (to Clk_Count[16])
                  --------
                    1.162   (19.8% logic, 80.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_239:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.613       R9C4A.Q1 to     R9C14B.CLK Clk_Count[16]
                  --------
                    2.684   (20.9% logic, 79.1% route), 2 logic levels.


Passed: The following path meets requirements by 0.411ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[1]  (to Clk_Count[16] +)

   Delay:               1.162ns  (19.8% logic, 80.2% route), 2 logic levels.

 Constraint Details:

      1.162ns physical path delay SLICE_277 to SLICE_239 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.764ns skew requirement (totaling 0.751ns) by 0.411ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_239:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.932      R9C15C.Q0 to      R9C14B.A0 TB_watchdog
CTOF_DEL    ---     0.099      R9C14B.A0 to      R9C14B.F0 SLICE_239
ROUTE         1     0.000      R9C14B.F0 to     R9C14B.DI0 TB_watchdog_s[1] (to Clk_Count[16])
                  --------
                    1.162   (19.8% logic, 80.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_239:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.613       R9C4A.Q1 to     R9C14B.CLK Clk_Count[16]
                  --------
                    2.684   (20.9% logic, 79.1% route), 2 logic levels.


Passed: The following path meets requirements by 0.415ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[6]  (to Clk_Count[16] +)

   Delay:               1.166ns  (19.7% logic, 80.3% route), 2 logic levels.

 Constraint Details:

      1.166ns physical path delay SLICE_277 to SLICE_237 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.764ns skew requirement (totaling 0.751ns) by 0.415ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.936      R9C15C.Q0 to      R9C14D.A1 TB_watchdog
CTOF_DEL    ---     0.099      R9C14D.A1 to      R9C14D.F1 SLICE_237
ROUTE         1     0.000      R9C14D.F1 to     R9C14D.DI1 TB_watchdog_s[6] (to Clk_Count[16])
                  --------
                    1.166   (19.7% logic, 80.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_237:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.613       R9C4A.Q1 to     R9C14D.CLK Clk_Count[16]
                  --------
                    2.684   (20.9% logic, 79.1% route), 2 logic levels.


Passed: The following path meets requirements by 0.415ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[4]  (to Clk_Count[16] +)

   Delay:               1.166ns  (19.7% logic, 80.3% route), 2 logic levels.

 Constraint Details:

      1.166ns physical path delay SLICE_277 to SLICE_238 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.764ns skew requirement (totaling 0.751ns) by 0.415ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.936      R9C15C.Q0 to      R9C14C.A1 TB_watchdog
CTOF_DEL    ---     0.099      R9C14C.A1 to      R9C14C.F1 SLICE_238
ROUTE         1     0.000      R9C14C.F1 to     R9C14C.DI1 TB_watchdog_s[4] (to Clk_Count[16])
                  --------
                    1.166   (19.7% logic, 80.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.613       R9C4A.Q1 to     R9C14C.CLK Clk_Count[16]
                  --------
                    2.684   (20.9% logic, 79.1% route), 2 logic levels.


Passed: The following path meets requirements by 0.415ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Clr_Count[22]  (from Clk_c +)
   Destination:    FF         Data in        TB_watchdog[3]  (to Clk_Count[16] +)

   Delay:               1.166ns  (19.7% logic, 80.3% route), 2 logic levels.

 Constraint Details:

      1.166ns physical path delay SLICE_277 to SLICE_238 meets
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
     -0.764ns skew requirement (totaling 0.751ns) by 0.415ns

 Physical Path Details:

      Data path SLICE_277 to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15C.CLK to      R9C15C.Q0 SLICE_277 (from Clk_c)
ROUTE        26     0.936      R9C15C.Q0 to      R9C14C.A0 TB_watchdog
CTOF_DEL    ---     0.099      R9C14C.A0 to      R9C14C.F0 SLICE_238
ROUTE         1     0.000      R9C14C.F0 to     R9C14C.DI0 TB_watchdog_s[3] (to Clk_Count[16])
                  --------
                    1.166   (19.7% logic, 80.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to SLICE_277:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_238:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to      R9C4A.CLK Clk_c
REG_DEL     ---     0.151      R9C4A.CLK to       R9C4A.Q1 SLICE_227
ROUTE         6     0.613       R9C4A.Q1 to     R9C14C.CLK Clk_Count[16]
                  --------
                    2.684   (20.9% logic, 79.1% route), 2 logic levels.


================================================================================
Preference: FREQUENCY NET "un3_tb_pluse_q2_buf" 399.840000 MHz ;
            1 item scored, 1 timing error detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 1.001ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U5/Q  (from Clk_c +)
   Destination:    FF         Data in        SPulse_Check  (to un3_tb_pluse_q2_buf +)

   Delay:               0.706ns  (18.6% logic, 81.4% route), 1 logic levels.

 Constraint Details:

      0.706ns physical path delay U5/SLICE_275 to SLICE_274 exceeds
      (delay constraint based on source clock period of 3.711ns and destination clock period of 2.501ns)
      0.000ns LSRREC_HLD and
      0.000ns delay constraint less
     -1.707ns skew requirement (totaling 1.707ns) by 1.001ns

 Physical Path Details:

      Data path U5/SLICE_275 to SLICE_274:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R9C15D.CLK to      R9C15D.Q0 U5/SLICE_275 (from Clk_c)
ROUTE        20     0.575      R9C15D.Q0 to    R11C13B.LSR TB_Pluse_Q1 (to un3_tb_pluse_q2_buf)
                  --------
                    0.706   (18.6% logic, 81.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clk to U5/SLICE_275:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15D.CLK Clk_c
                  --------
                    1.920   (21.3% logic, 78.7% route), 1 logic levels.

      Destination Clock Path Clk to SLICE_274:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.409         31.PAD to       31.PADDI Clk
ROUTE       138     1.511       31.PADDI to     R9C15C.CLK Clk_c
REG_DEL     ---     0.151     R9C15C.CLK to      R9C15C.Q0 SLICE_277
ROUTE        26     1.194      R9C15C.Q0 to     R11C13D.C1 TB_watchdog
CTOF_DEL    ---     0.174     R11C13D.C1 to     R11C13D.F1 SLICE_338
ROUTE         1     0.188     R11C13D.F1 to    R11C13B.CLK un3_tb_pluse_q2_buf
                  --------
                    3.627   (20.2% logic, 79.8% route), 3 logic levels.


================================================================================
Preference: FREQUENCY NET "U3/Clk_10ms[17]" 335.909000 MHz ;
            84 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[7]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[7]  (to U3/Clk_10ms[17] +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay U3/SLICE_55 to U3/SLICE_55 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path U3/SLICE_55 to U3/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C5A.CLK to      R11C5A.Q0 U3/SLICE_55 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C5A.Q0 to      R11C5A.A0 U3/Count_stop[7]
CTOF_DEL    ---     0.099      R11C5A.A0 to      R11C5A.F0 U3/SLICE_55
ROUTE         1     0.000      R11C5A.F0 to     R11C5A.DI0 U3/Count_stop_s[7] (to U3/Clk_10ms[17])
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C5A.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C5A.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[5]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[5]  (to U3/Clk_10ms[17] +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay U3/SLICE_56 to U3/SLICE_56 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path U3/SLICE_56 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4D.CLK to      R11C4D.Q0 U3/SLICE_56 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4D.Q0 to      R11C4D.A0 U3/Count_stop[5]
CTOF_DEL    ---     0.099      R11C4D.A0 to      R11C4D.F0 U3/SLICE_56
ROUTE         1     0.000      R11C4D.F0 to     R11C4D.DI0 U3/Count_stop_s[5] (to U3/Clk_10ms[17])
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4D.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4D.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[6]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[6]  (to U3/Clk_10ms[17] +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay U3/SLICE_56 to U3/SLICE_56 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path U3/SLICE_56 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4D.CLK to      R11C4D.Q1 U3/SLICE_56 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4D.Q1 to      R11C4D.A1 U3/Count_stop[6]
CTOF_DEL    ---     0.099      R11C4D.A1 to      R11C4D.F1 U3/SLICE_56
ROUTE         1     0.000      R11C4D.F1 to     R11C4D.DI1 U3/Count_stop_s[6] (to U3/Clk_10ms[17])
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4D.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4D.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[1]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[1]  (to U3/Clk_10ms[17] +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay U3/SLICE_58 to U3/SLICE_58 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path U3/SLICE_58 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4B.CLK to      R11C4B.Q0 U3/SLICE_58 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4B.Q0 to      R11C4B.A0 U3/Count_stop[1]
CTOF_DEL    ---     0.099      R11C4B.A0 to      R11C4B.F0 U3/SLICE_58
ROUTE         1     0.000      R11C4B.F0 to     R11C4B.DI0 U3/Count_stop_s[1] (to U3/Clk_10ms[17])
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[2]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[2]  (to U3/Clk_10ms[17] +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay U3/SLICE_58 to U3/SLICE_58 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path U3/SLICE_58 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4B.CLK to      R11C4B.Q1 U3/SLICE_58 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4B.Q1 to      R11C4B.A1 U3/Count_stop[2]
CTOF_DEL    ---     0.099      R11C4B.A1 to      R11C4B.F1 U3/SLICE_58
ROUTE         1     0.000      R11C4B.F1 to     R11C4B.DI1 U3/Count_stop_s[2] (to U3/Clk_10ms[17])
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4B.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[4]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[4]  (to U3/Clk_10ms[17] +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay U3/SLICE_57 to U3/SLICE_57 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path U3/SLICE_57 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4C.CLK to      R11C4C.Q1 U3/SLICE_57 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4C.Q1 to      R11C4C.A1 U3/Count_stop[4]
CTOF_DEL    ---     0.099      R11C4C.A1 to      R11C4C.F1 U3/SLICE_57
ROUTE         1     0.000      R11C4C.F1 to     R11C4C.DI1 U3/Count_stop_s[4] (to U3/Clk_10ms[17])
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4C.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4C.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[3]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[3]  (to U3/Clk_10ms[17] +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay U3/SLICE_57 to U3/SLICE_57 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path U3/SLICE_57 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4C.CLK to      R11C4C.Q0 U3/SLICE_57 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4C.Q0 to      R11C4C.A0 U3/Count_stop[3]
CTOF_DEL    ---     0.099      R11C4C.A0 to      R11C4C.F0 U3/SLICE_57
ROUTE         1     0.000      R11C4C.F0 to     R11C4C.DI0 U3/Count_stop_s[3] (to U3/Clk_10ms[17])
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4C.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4C.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[0]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[0]  (to U3/Clk_10ms[17] +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay U3/SLICE_59 to U3/SLICE_59 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path U3/SLICE_59 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4A.CLK to      R11C4A.Q1 U3/SLICE_59 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4A.Q1 to      R11C4A.A1 U3/Count_stop[0]
CTOF_DEL    ---     0.099      R11C4A.A1 to      R11C4A.F1 U3/SLICE_59
ROUTE         1     0.000      R11C4A.F1 to     R11C4A.DI1 U3/Count_stop_s[0] (to U3/Clk_10ms[17])
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4A.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.494ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[3]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[4]  (to U3/Clk_10ms[17] +)

   Delay:               0.481ns  (73.2% logic, 26.8% route), 2 logic levels.

 Constraint Details:

      0.481ns physical path delay U3/SLICE_57 to U3/SLICE_57 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.494ns

 Physical Path Details:

      Data path U3/SLICE_57 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4C.CLK to      R11C4C.Q0 U3/SLICE_57 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4C.Q0 to      R11C4C.A0 U3/Count_stop[3]
CTOF1_DEL   ---     0.221      R11C4C.A0 to      R11C4C.F1 U3/SLICE_57
ROUTE         1     0.000      R11C4C.F1 to     R11C4C.DI1 U3/Count_stop_s[4] (to U3/Clk_10ms[17])
                  --------
                    0.481   (73.2% logic, 26.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4C.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_57:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4C.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.494ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U3/Count_stop[5]  (from U3/Clk_10ms[17] +)
   Destination:    FF         Data in        U3/Count_stop[6]  (to U3/Clk_10ms[17] +)

   Delay:               0.481ns  (73.2% logic, 26.8% route), 2 logic levels.

 Constraint Details:

      0.481ns physical path delay U3/SLICE_56 to U3/SLICE_56 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.494ns

 Physical Path Details:

      Data path U3/SLICE_56 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R11C4D.CLK to      R11C4D.Q0 U3/SLICE_56 (from U3/Clk_10ms[17])
ROUTE         2     0.129      R11C4D.Q0 to      R11C4D.A0 U3/Count_stop[5]
CTOF1_DEL   ---     0.221      R11C4D.A0 to      R11C4D.F1 U3/SLICE_56
ROUTE         1     0.000      R11C4D.F1 to     R11C4D.DI1 U3/Count_stop_s[6] (to U3/Clk_10ms[17])
                  --------
                    0.481   (73.2% logic, 26.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path U3/SLICE_45 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4D.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path U3/SLICE_45 to U3/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     0.871     R10C13B.Q0 to     R11C4D.CLK U3/Clk_10ms[17]
                  --------
                    0.871   (0.0% logic, 100.0% route), 0 logic levels.


================================================================================
Preference: FREQUENCY NET "LaserPulse_Sig" 319.693000 MHz ;
            296 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[15]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[15]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_218 to SLICE_218 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_218 to SLICE_218:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R4C10A.CLK to      R4C10A.Q0 SLICE_218 (from LaserPulse_Sig)
ROUTE         2     0.129      R4C10A.Q0 to      R4C10A.A0 SPulseCount[15]
CTOF_DEL    ---     0.099      R4C10A.A0 to      R4C10A.F0 SLICE_218
ROUTE         1     0.000      R4C10A.F0 to     R4C10A.DI0 SPulseCount_s[15] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_218:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to     R4C10A.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_218:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to     R4C10A.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[14]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[14]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_219 to SLICE_219 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_219 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C9D.CLK to       R4C9D.Q1 SLICE_219 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C9D.Q1 to       R4C9D.A1 SPulseCount[14]
CTOF_DEL    ---     0.099       R4C9D.A1 to       R4C9D.F1 SLICE_219
ROUTE         1     0.000       R4C9D.F1 to      R4C9D.DI1 SPulseCount_s[14] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9D.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9D.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[13]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[13]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_219 to SLICE_219 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_219 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C9D.CLK to       R4C9D.Q0 SLICE_219 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C9D.Q0 to       R4C9D.A0 SPulseCount[13]
CTOF_DEL    ---     0.099       R4C9D.A0 to       R4C9D.F0 SLICE_219
ROUTE         1     0.000       R4C9D.F0 to      R4C9D.DI0 SPulseCount_s[13] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9D.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9D.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[11]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[11]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_220 to SLICE_220 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_220 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C9C.CLK to       R4C9C.Q0 SLICE_220 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C9C.Q0 to       R4C9C.A0 SPulseCount[11]
CTOF_DEL    ---     0.099       R4C9C.A0 to       R4C9C.F0 SLICE_220
ROUTE         1     0.000       R4C9C.F0 to      R4C9C.DI0 SPulseCount_s[11] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9C.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9C.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[12]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[12]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_220 to SLICE_220 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_220 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C9C.CLK to       R4C9C.Q1 SLICE_220 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C9C.Q1 to       R4C9C.A1 SPulseCount[12]
CTOF_DEL    ---     0.099       R4C9C.A1 to       R4C9C.F1 SLICE_220
ROUTE         1     0.000       R4C9C.F1 to      R4C9C.DI1 SPulseCount_s[12] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9C.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9C.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[9]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[9]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_221 to SLICE_221 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_221 to SLICE_221:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C9B.CLK to       R4C9B.Q0 SLICE_221 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C9B.Q0 to       R4C9B.A0 SPulseCount[9]
CTOF_DEL    ---     0.099       R4C9B.A0 to       R4C9B.F0 SLICE_221
ROUTE         1     0.000       R4C9B.F0 to      R4C9B.DI0 SPulseCount_s[9] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_221:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9B.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_221:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9B.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[10]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[10]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_221 to SLICE_221 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_221 to SLICE_221:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C9B.CLK to       R4C9B.Q1 SLICE_221 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C9B.Q1 to       R4C9B.A1 SPulseCount[10]
CTOF_DEL    ---     0.099       R4C9B.A1 to       R4C9B.F1 SLICE_221
ROUTE         1     0.000       R4C9B.F1 to      R4C9B.DI1 SPulseCount_s[10] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_221:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9B.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_221:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9B.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[8]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[8]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_222 to SLICE_222 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_222 to SLICE_222:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C9A.CLK to       R4C9A.Q1 SLICE_222 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C9A.Q1 to       R4C9A.A1 SPulseCount[8]
CTOF_DEL    ---     0.099       R4C9A.A1 to       R4C9A.F1 SLICE_222
ROUTE         1     0.000       R4C9A.F1 to      R4C9A.DI1 SPulseCount_s[8] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_222:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9A.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_222:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9A.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[7]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[7]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_222 to SLICE_222 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_222 to SLICE_222:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C9A.CLK to       R4C9A.Q0 SLICE_222 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C9A.Q0 to       R4C9A.A0 SPulseCount[7]
CTOF_DEL    ---     0.099       R4C9A.A0 to       R4C9A.F0 SLICE_222
ROUTE         1     0.000       R4C9A.F0 to      R4C9A.DI0 SPulseCount_s[7] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_222:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9A.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_222:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C9A.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              SPulseCount[5]  (from LaserPulse_Sig -)
   Destination:    FF         Data in        SPulseCount[5]  (to LaserPulse_Sig -)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_223 to SLICE_223 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_223 to SLICE_223:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R4C8D.CLK to       R4C8D.Q0 SLICE_223 (from LaserPulse_Sig)
ROUTE         2     0.129       R4C8D.Q0 to       R4C8D.A0 SPulseCount[5]
CTOF_DEL    ---     0.099       R4C8D.A0 to       R4C8D.F0 SLICE_223
ROUTE         1     0.000       R4C8D.F0 to      R4C8D.DI0 SPulseCount_s[5] (to LaserPulse_Sig)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_390 to SLICE_223:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C8D.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_390 to SLICE_223:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.159      R2C12A.F0 to      R4C8D.CLK LaserPulse_Sig
                  --------
                    1.159   (0.0% logic, 100.0% route), 0 logic levels.


================================================================================
Preference: FREQUENCY NET "Clk_Count[13]" 327.439000 MHz ;
            88 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U2/Count[0]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U2/Count[0]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U2/SLICE_203 to U2/SLICE_203 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U2/SLICE_203 to U2/SLICE_203:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R7C15A.CLK to      R7C15A.Q1 U2/SLICE_203 (from Clk_Count[13])
ROUTE         1     0.127      R7C15A.Q1 to      R7C15A.A1 U2/Count[0]
CTOF_DEL    ---     0.099      R7C15A.A1 to      R7C15A.F1 U2/SLICE_203
ROUTE         1     0.000      R7C15A.F1 to     R7C15A.DI1 U2/un1_Count_1_cry_0_0_S1 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U2/SLICE_203:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to     R7C15A.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U2/SLICE_203:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to     R7C15A.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[3]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[3]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U1/SLICE_206 to U1/SLICE_206 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U1/SLICE_206 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R11C12C.CLK to     R11C12C.Q0 U1/SLICE_206 (from Clk_Count[13])
ROUTE         1     0.127     R11C12C.Q0 to     R11C12C.A0 U1/Count[3]
CTOF_DEL    ---     0.099     R11C12C.A0 to     R11C12C.F0 U1/SLICE_206
ROUTE         1     0.000     R11C12C.F0 to    R11C12C.DI0 U1/un1_Count_1_cry_3_0_S0_0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12C.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12C.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[1]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[1]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U1/SLICE_207 to U1/SLICE_207 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U1/SLICE_207 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R11C12B.CLK to     R11C12B.Q0 U1/SLICE_207 (from Clk_Count[13])
ROUTE         1     0.127     R11C12B.Q0 to     R11C12B.A0 U1/Count[1]
CTOF_DEL    ---     0.099     R11C12B.A0 to     R11C12B.F0 U1/SLICE_207
ROUTE         1     0.000     R11C12B.F0 to    R11C12B.DI0 U1/un1_Count_1_cry_1_0_S0_0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12B.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12B.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[6]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[6]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U1/SLICE_205 to U1/SLICE_205 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U1/SLICE_205 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R11C12D.CLK to     R11C12D.Q1 U1/SLICE_205 (from Clk_Count[13])
ROUTE         1     0.127     R11C12D.Q1 to     R11C12D.A1 U1/Count[6]
CTOF_DEL    ---     0.099     R11C12D.A1 to     R11C12D.F1 U1/SLICE_205
ROUTE         1     0.000     R11C12D.F1 to    R11C12D.DI1 U1/un1_Count_1_cry_5_0_S1_0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12D.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12D.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[5]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[5]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U1/SLICE_205 to U1/SLICE_205 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U1/SLICE_205 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R11C12D.CLK to     R11C12D.Q0 U1/SLICE_205 (from Clk_Count[13])
ROUTE         1     0.127     R11C12D.Q0 to     R11C12D.A0 U1/Count[5]
CTOF_DEL    ---     0.099     R11C12D.A0 to     R11C12D.F0 U1/SLICE_205
ROUTE         1     0.000     R11C12D.F0 to    R11C12D.DI0 U1/un1_Count_1_cry_5_0_S0_0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12D.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_205:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12D.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[2]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[2]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U1/SLICE_207 to U1/SLICE_207 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U1/SLICE_207 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R11C12B.CLK to     R11C12B.Q1 U1/SLICE_207 (from Clk_Count[13])
ROUTE         1     0.127     R11C12B.Q1 to     R11C12B.A1 U1/Count[2]
CTOF_DEL    ---     0.099     R11C12B.A1 to     R11C12B.F1 U1/SLICE_207
ROUTE         1     0.000     R11C12B.F1 to    R11C12B.DI1 U1/un1_Count_1_cry_1_0_S1_0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12B.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_207:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12B.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[0]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[0]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U1/SLICE_208 to U1/SLICE_208 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U1/SLICE_208 to U1/SLICE_208:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R11C12A.CLK to     R11C12A.Q1 U1/SLICE_208 (from Clk_Count[13])
ROUTE         1     0.127     R11C12A.Q1 to     R11C12A.A1 U1/Count[0]
CTOF_DEL    ---     0.099     R11C12A.A1 to     R11C12A.F1 U1/SLICE_208
ROUTE         1     0.000     R11C12A.F1 to    R11C12A.DI1 U1/un1_Count_1_cry_0_0_S1_0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_208:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12A.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_208:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12A.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U2/Count[5]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U2/Count[5]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U2/SLICE_200 to U2/SLICE_200 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U2/SLICE_200 to U2/SLICE_200:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R7C15D.CLK to      R7C15D.Q0 U2/SLICE_200 (from Clk_Count[13])
ROUTE         1     0.127      R7C15D.Q0 to      R7C15D.A0 U2/Count[5]
CTOF_DEL    ---     0.099      R7C15D.A0 to      R7C15D.F0 U2/SLICE_200
ROUTE         1     0.000      R7C15D.F0 to     R7C15D.DI0 U2/un1_Count_1_cry_5_0_S0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U2/SLICE_200:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to     R7C15D.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U2/SLICE_200:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to     R7C15D.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U2/Count[3]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U2/Count[3]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U2/SLICE_201 to U2/SLICE_201 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U2/SLICE_201 to U2/SLICE_201:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R7C15C.CLK to      R7C15C.Q0 U2/SLICE_201 (from Clk_Count[13])
ROUTE         1     0.127      R7C15C.Q0 to      R7C15C.A0 U2/Count[3]
CTOF_DEL    ---     0.099      R7C15C.A0 to      R7C15C.F0 U2/SLICE_201
ROUTE         1     0.000      R7C15C.F0 to     R7C15C.DI0 U2/un1_Count_1_cry_3_0_S0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U2/SLICE_201:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to     R7C15C.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U2/SLICE_201:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to     R7C15C.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              U1/Count[4]  (from Clk_Count[13] +)
   Destination:    FF         Data in        U1/Count[4]  (to Clk_Count[13] +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay U1/SLICE_206 to U1/SLICE_206 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path U1/SLICE_206 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R11C12C.CLK to     R11C12C.Q1 U1/SLICE_206 (from Clk_Count[13])
ROUTE         1     0.127     R11C12C.Q1 to     R11C12C.A1 U1/Count[4]
CTOF_DEL    ---     0.099     R11C12C.A1 to     R11C12C.F1 U1/SLICE_206
ROUTE         1     0.000     R11C12C.F1 to    R11C12C.DI1 U1/un1_Count_1_cry_3_0_S1_0 (to Clk_Count[13])
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path SLICE_228 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12C.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path SLICE_228 to U1/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        11     1.666       R9C3D.Q0 to    R11C12C.CLK Clk_Count[13]
                  --------
                    1.666   (0.0% logic, 100.0% route), 0 logic levels.


================================================================================
Preference: FREQUENCY NET "FSMC_NADV_c" 399.840000 MHz ;
            16 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[4]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[4]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_266 to SLICE_266 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_266 to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C7A.CLK to       R9C7A.Q0 SLICE_266 (from FSMC_NADV_c)
ROUTE         2     0.129       R9C7A.Q0 to       R9C7A.A0 FSMC_Add[4]
CTOF_DEL    ---     0.099       R9C7A.A0 to       R9C7A.F0 SLICE_266
ROUTE         1     0.000       R9C7A.F0 to      R9C7A.DI0 FSMC_Add_0[4] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to      R9C7A.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to      R9C7A.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[5]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[5]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_266 to SLICE_266 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_266 to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131      R9C7A.CLK to       R9C7A.Q1 SLICE_266 (from FSMC_NADV_c)
ROUTE         2     0.129       R9C7A.Q1 to       R9C7A.A1 FSMC_Add[5]
CTOF_DEL    ---     0.099       R9C7A.A1 to       R9C7A.F1 SLICE_266
ROUTE         1     0.000       R9C7A.F1 to      R9C7A.DI1 FSMC_Add_0[5] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to      R9C7A.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_266:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to      R9C7A.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[8]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[8]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_268 to SLICE_268 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_268 to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R10C7D.CLK to      R10C7D.Q0 SLICE_268 (from FSMC_NADV_c)
ROUTE         2     0.129      R10C7D.Q0 to      R10C7D.A0 FSMC_Add[8]
CTOF_DEL    ---     0.099      R10C7D.A0 to      R10C7D.F0 SLICE_268
ROUTE         1     0.000      R10C7D.F0 to     R10C7D.DI0 FSMC_Add_0[8] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.305        1.PADDI to     R10C7D.CLK FSMC_NADV_c
                  --------
                    1.305   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.305        1.PADDI to     R10C7D.CLK FSMC_NADV_c
                  --------
                    1.305   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[9]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[9]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_268 to SLICE_268 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_268 to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R10C7D.CLK to      R10C7D.Q1 SLICE_268 (from FSMC_NADV_c)
ROUTE         2     0.129      R10C7D.Q1 to      R10C7D.A1 FSMC_Add[9]
CTOF_DEL    ---     0.099      R10C7D.A1 to      R10C7D.F1 SLICE_268
ROUTE         1     0.000      R10C7D.F1 to     R10C7D.DI1 FSMC_Add_0[9] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.305        1.PADDI to     R10C7D.CLK FSMC_NADV_c
                  --------
                    1.305   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_268:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.305        1.PADDI to     R10C7D.CLK FSMC_NADV_c
                  --------
                    1.305   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[10]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[10]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_269 to SLICE_269 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_269 to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R10C6B.CLK to      R10C6B.Q0 SLICE_269 (from FSMC_NADV_c)
ROUTE         2     0.129      R10C6B.Q0 to      R10C6B.A0 FSMC_Add[10]
CTOF_DEL    ---     0.099      R10C6B.A0 to      R10C6B.F0 SLICE_269
ROUTE         1     0.000      R10C6B.F0 to     R10C6B.DI0 FSMC_Add_0[10] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to     R10C6B.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to     R10C6B.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[11]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[11]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_269 to SLICE_269 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_269 to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R10C6B.CLK to      R10C6B.Q1 SLICE_269 (from FSMC_NADV_c)
ROUTE         2     0.129      R10C6B.Q1 to      R10C6B.A1 FSMC_Add[11]
CTOF_DEL    ---     0.099      R10C6B.A1 to      R10C6B.F1 SLICE_269
ROUTE         1     0.000      R10C6B.F1 to     R10C6B.DI1 FSMC_Add_0[11] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to     R10C6B.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_269:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to     R10C6B.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[12]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[12]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_270 to SLICE_270 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_270 to SLICE_270:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R10C7A.CLK to      R10C7A.Q0 SLICE_270 (from FSMC_NADV_c)
ROUTE         2     0.129      R10C7A.Q0 to      R10C7A.A0 FSMC_Add[12]
CTOF_DEL    ---     0.099      R10C7A.A0 to      R10C7A.F0 SLICE_270
ROUTE         1     0.000      R10C7A.F0 to     R10C7A.DI0 FSMC_Add_0[12] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_270:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.305        1.PADDI to     R10C7A.CLK FSMC_NADV_c
                  --------
                    1.305   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_270:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.305        1.PADDI to     R10C7A.CLK FSMC_NADV_c
                  --------
                    1.305   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[13]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[13]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_270 to SLICE_270 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_270 to SLICE_270:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R10C7A.CLK to      R10C7A.Q1 SLICE_270 (from FSMC_NADV_c)
ROUTE         2     0.129      R10C7A.Q1 to      R10C7A.A1 FSMC_Add[13]
CTOF_DEL    ---     0.099      R10C7A.A1 to      R10C7A.F1 SLICE_270
ROUTE         1     0.000      R10C7A.F1 to     R10C7A.DI1 FSMC_Add_0[13] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_270:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.305        1.PADDI to     R10C7A.CLK FSMC_NADV_c
                  --------
                    1.305   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_270:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.305        1.PADDI to     R10C7A.CLK FSMC_NADV_c
                  --------
                    1.305   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[14]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[14]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_271 to SLICE_271 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_271 to SLICE_271:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R10C7B.CLK to      R10C7B.Q0 SLICE_271 (from FSMC_NADV_c)
ROUTE         2     0.129      R10C7B.Q0 to      R10C7B.A0 FSMC_Add[14]
CTOF_DEL    ---     0.099      R10C7B.A0 to      R10C7B.F0 SLICE_271
ROUTE         1     0.000      R10C7B.F0 to     R10C7B.DI0 FSMC_Add_0[14] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_271:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to     R10C7B.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_271:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to     R10C7B.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FSMC_Add[15]  (from FSMC_NADV_c +)
   Destination:    FF         Data in        FSMC_Add[15]  (to FSMC_NADV_c +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay SLICE_271 to SLICE_271 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path SLICE_271 to SLICE_271:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R10C7B.CLK to      R10C7B.Q1 SLICE_271 (from FSMC_NADV_c)
ROUTE         2     0.129      R10C7B.Q1 to      R10C7B.A1 FSMC_Add[15]
CTOF_DEL    ---     0.099      R10C7B.A1 to      R10C7B.F1 SLICE_271
ROUTE         1     0.000      R10C7B.F1 to     R10C7B.DI1 FSMC_Add_0[15] (to FSMC_NADV_c)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path FSMC_NADV to SLICE_271:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to     R10C7B.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path FSMC_NADV to SLICE_271:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE         8     1.295        1.PADDI to     R10C7B.CLK FSMC_NADV_c
                  --------
                    1.295   (0.0% logic, 100.0% route), 0 logic levels.

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "Clk_c" 269.469000 MHz ;  |     0.000 ns|     0.370 ns|   2  
                                        |             |             |
FREQUENCY NET "Clk_Count[16]"           |             |             |
399.840000 MHz ;                        |     0.000 ns|     0.211 ns|   2  
                                        |             |             |
FREQUENCY NET "un3_tb_pluse_q2_buf"     |             |             |
399.840000 MHz ;                        |     0.000 ns|    -1.001 ns|   1 *
                                        |             |             |
FREQUENCY NET "U3/Clk_10ms[17]"         |             |             |
335.909000 MHz ;                        |     0.000 ns|     0.372 ns|   2  
                                        |             |             |
FREQUENCY NET "LaserPulse_Sig"          |             |             |
319.693000 MHz ;                        |     0.000 ns|     0.372 ns|   2  
                                        |             |             |
FREQUENCY NET "Clk_Count[13]"           |             |             |
327.439000 MHz ;                        |     0.000 ns|     0.370 ns|   2  
                                        |             |             |
FREQUENCY NET "FSMC_NADV_c" 399.840000  |             |             |
MHz ;                                   |     0.000 ns|     0.372 ns|   2  
                                        |             |             |
----------------------------------------------------------------------------


1 preference(marked by "*" above) not met.

----------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
----------------------------------------------------------------------------
TB_Pluse_Q1                             |      20|       1|    100.00%
                                        |        |        |
----------------------------------------------------------------------------


Clock Domains Analysis
------------------------

Found 8 clocks:

Clock Domain: un3_tb_pluse_q2_buf   Source: SLICE_338.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: Clk_c   Source: Clk.PAD
      Covered under: FREQUENCY NET "un3_tb_pluse_q2_buf" 399.840000 MHz ;   Transfers: 1

Clock Domain: U3/Clk_10ms[17]   Source: U3/SLICE_45.Q0   Loads: 8
   Covered under: FREQUENCY NET "U3/Clk_10ms[17]" 335.909000 MHz ;

   Data transfers from:
   Clock Domain: FSMC_NWE_c   Source: FSMC_NWE.PAD
      Not reported because source and destination domains are unrelated.

Clock Domain: LaserPulse_Sig   Source: SLICE_390.F0   Loads: 11
   Covered under: FREQUENCY NET "LaserPulse_Sig" 319.693000 MHz ;

   Data transfers from:
   Clock Domain: FSMC_NWE_c   Source: FSMC_NWE.PAD
      Not reported because source and destination domains are unrelated.

Clock Domain: FSMC_NWE_c   Source: FSMC_NWE.PAD   Loads: 74
   No transfer within this clock domain is found

Clock Domain: FSMC_NADV_c   Source: FSMC_NADV.PAD   Loads: 8
   Covered under: FREQUENCY NET "FSMC_NADV_c" 399.840000 MHz ;

Clock Domain: Clk_c   Source: Clk.PAD   Loads: 138
   Covered under: FREQUENCY NET "Clk_c" 269.469000 MHz ;

   Data transfers from:
   Clock Domain: U3/Clk_10ms[17]   Source: U3/SLICE_45.Q0
      Covered under: FREQUENCY NET "Clk_c" 269.469000 MHz ;   Transfers: 1

   Clock Domain: LaserPulse_Sig   Source: SLICE_390.F0
      Covered under: FREQUENCY NET "Clk_c" 269.469000 MHz ;   Transfers: 1

   Clock Domain: FSMC_NWE_c   Source: FSMC_NWE.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

   Clock Domain: Clk_Count[16]   Source: SLICE_227.Q1
      Covered under: FREQUENCY NET "Clk_c" 269.469000 MHz ;   Transfers: 1

Clock Domain: Clk_Count[16]   Source: SLICE_227.Q1   Loads: 6
   Covered under: FREQUENCY NET "Clk_Count[16]" 399.840000 MHz ;

   Data transfers from:
   Clock Domain: Clk_c   Source: Clk.PAD
      Covered under: FREQUENCY NET "Clk_Count[16]" 399.840000 MHz ;   Transfers: 1

Clock Domain: Clk_Count[13]   Source: SLICE_228.Q0   Loads: 11
   Covered under: FREQUENCY NET "Clk_Count[13]" 327.439000 MHz ;


Timing summary (Hold):
---------------

Timing errors: 1  Score: 1001
Cumulative negative slack: 1001

Constraints cover 18092 paths, 15 nets, and 1501 connections (65.09% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 4506 (setup), 1 (hold)
Score: 41478171 (setup), 1001 (hold)
Cumulative negative slack: 41479172 (41478171+1001)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------


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